Hardware Engineer at Cisco — VLSI, RTL design & verification by day.
I also design, build, and launch AI-powered products end to end. Napkin sketch → shipped.
Hardware & Verification
AI & Product
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My core discipline. I ship a new hardware design every day across four portfolios — each one parameterized RTL with a self-checking testbench simulated end-to-end in Icarus Verilog. Below is every project, by track.
🔁 RTL Design · RTL-Projects-Everyday 
Synthesizable digital blocks — datapaths, protocol controllers, and pipelined arithmetic — each with a golden-model, self-checking testbench.
| # | Design | What it demonstrates |
|---|---|---|
| 1 | Parameterized Synchronous FIFO | Read/write pointers, occupancy counter, full/empty flags |
| 2 | Round-Robin Arbiter | Fair rotating priority, one-hot grant, wrap-around masking |
| 3 | Configurable SPI Master | All 4 CPOL/CPHA modes, programmable SCLK divider, full-duplex FSM |
| 4 | Asynchronous (dual-clock) FIFO | CDC with Gray-code pointers and two-flop synchronizers |
| 5 | Configurable UART (TX + RX) | 8-N-1 framing, run-time baud divider, mid-bit sampling, loopback TB |
| 6 | Sequential Integer Divider | Restoring shift-subtract, multicycle FSM, quotient + remainder |
| 7 | AXI4-Lite Slave Register Block | Full 5-channel handshakes, WSTRB, OKAY/SLVERR, RW/RO/W1C regs |
| 8 | I²C Master Controller | Open-drain bus, START/STOP, 7-bit addr, per-byte ACK/NACK, clock-stretch |
| 9 | Pipelined CORDIC Sine/Cosine | Multiplier-free, fully-unrolled pipeline, Q2.13 fixed-point |
| 10 | SECDED Hamming ECC Codec | (72,64) single-correct/double-detect, syndrome decode, pipelined |
| 11 | Pipelined Bitonic Sorting Network | Data-independent compare-exchange, 1 vector/clock throughput |
| 12 | Pipelined Radix-4 Booth Multiplier | Booth recoding + Wallace CSA reduction tree, 4-stage pipeline |
| 13 | Pipelined IEEE-754 FP Adder (binary32) | Round-to-nearest-even, subnormals, Inf/NaN, 3-stage pipeline |
🧪 Design Verification · Design-Verification-Projects-Everyday 
Full UVM environments — agents, scoreboards, layered + virtual sequences, functional coverage, and protocol SVA.
| # | Environment | What it verifies |
|---|---|---|
| 1 | Constrained-Random FIFO Scoreboard | Golden-model scoreboard, functional coverage, SVA assertions |
| 2 | UVM APB4 Register File | Full UVM agent, virtual sequencer, coverage, APB protocol SVA |
| 3 | UVM AXI4-Lite Register Block | 5-channel agent, layered + virtual sequences, AXI4-Lite SVA |
| 4 | UVM UART Environment | TX + RX agents, byte-reconstructing monitors, data×baud coverage |
| 5 | UVM RAL Demo | uvm_reg model, front/back-door access, bit-bash & reset sequences |
| 6 | UVM Packet-Router | Store-and-forward 1→N, per-port FIFO scoreboard, backpressure corners |
| 7 | UVM Round-Robin Arbiter | Fairness / anti-starvation checking, one-hot grant SVA |
| 8 | UVM Async FIFO (CDC) | Dual-clock agents, order + integrity across the CDC, Gray-code SVA |
| 9 | UVM ALU Functional Coverage | 8-op ALU, opcode×flag cross coverage, flag-correctness SVA |
| 10 | UVM AXI4-Stream Skid Buffer | Lossless in-order scoreboard, TKEEP/TLAST, stream-handshake SVA |
| 11 | UVM SPI Master | All 4 modes, full-duplex golden scoreboard, mode×divider coverage |
🧮 Computer Architecture · Computer-Architecture-Projects-Everyday 
A RISC-V core built bottom-up, plus the microarchitecture that makes real CPUs fast — caches, predictors, TLBs, and store buffers.
| # | Build | What it implements |
|---|---|---|
| 1 | Single-Cycle RV32I ALU | RV32I ops, signed vs. unsigned compare, logical vs. arithmetic shift |
| 2 | RV32I Register File (2R / 1W) | x0 hardwired to zero, synchronous write, WB→ID write-forwarding |
| 3 | RV32I Decoder + Immediate Gen | Control decode, I/S/B/U/J immediates, ALU-control mapping |
| 4 | RV32I Load/Store Unit + Data Mem | Byte-addressable little-endian, lb/lh/lw/…, sign/zero extension |
| 5 | Single-Cycle RV32I Core | Full integration, branch + jal/jalr, checked vs. an ISS golden trace |
| 6 | Bimodal 2-bit Branch Predictor | PC-indexed PHT, saturating-counter FSM, mispredict hysteresis |
| 7 | Direct-Mapped Write-Back Cache | Write-allocate, dirty eviction, miss-handling FSM |
| 8 | Radix-4 Booth Signed Multiplier | 2 bits/cycle recoding, add/shift accumulator, handshake FSM |
| 9 | Round-Robin Arbiter | Rotating priority, provable no-starvation bound, one-hot grant |
| 10 | Fully-Associative TLB (True-LRU) | VPN→PPN CAM lookup, age-matrix LRU, single-page invalidate + sfence |
| 11 | Store Buffer + Store-to-Load Forwarding | Circular store queue, youngest-match forwarding, in-order drain |
⚙️ Hardware/Software Co-Design · Hardware-Software-Codesign-Projects-Everyday 
Where hardware meets software: parameterized accelerators with real HW/SW interfaces, C firmware that drives them, and self-checking differential verification against a software reference.
| # | Accelerator | Result |
|---|---|---|
| 1 | FIR Stream Accelerator — transposed-form FIR, 8 MAC/cycle, AXI4-Lite control + AXI4-Stream data, C firmware | ~1 sample/clock, 7.88× over a scalar baseline, 0 mismatches across a 1354-sample differential test |
| Project | What it is |
|---|---|
| LC3 (UVM) | Constrained-random, coverage-driven UVM testbench verifying an LC-3 processor architecture |
| University-Projects | RTL, testbenches, and simulations across SystemVerilog, VHDL, and Verilog |
| Verilog-Projects | Verilog digital-logic and RTL design projects with simulation |
Off the clock, I ship AI-powered products end to end — real retrieval pipelines, multi-agent orchestration, payments, and full-stack apps put in front of users.
| Project | Why it's hard | Stack |
|---|---|---|
| 🛡️ TrustDraft | Auto-drafts SIG/CAIQ security questionnaires with a BM25 + LLM retrieval pipeline and per-answer confidence scoring. | Python FastAPI React TS SQLite Docker |
| 📈 Company-Analysis-Agent | Multi-agent system that fans out across live web sources, then reconciles them into an investment thesis + buy/hold/sell. | FastAPI React/TS Composio Nebius Tavily |
| The most feature-dense full-stack app: Postgres, Stripe payments, Firebase auth, PDF itinerary export. | React/TS Drizzle Postgres Stripe OpenAI |
| Project | One-liner |
|---|---|
| PreMortem | Red-team & pre-mortem review that stress-tests your decision docs before you commit. |
| StudySection | A mock grant-review panel that critiques your Specific Aims like a real study section. |
| BetaReader | Reader-persona developmental critique that reads your fiction like your target audience. |
| ScopeGuard | Flags freelance scope creep, estimates change orders, and drafts client replies. |
| Calibrate | Decision journal that scores confidence vs. reality (Brier/calibration) and coaches your next call. |
| Untangle | Thinking partner that reframes a dilemma and hands you one 10-minute next step. |
| NegotiateIQ | Salary-negotiation simulator against an AI hiring manager, with a scored debrief. |
| MicroMentor-AI | Daily 15-minute AI micro-lessons with reflections, feedback, and streaks. |
| Analogy-Forge | Explains hard concepts by mapping them onto a hobby you already understand. |
| Name-That-Feeling | Turns a vague feeling into a precise emotion word plus a reflection prompt. |
| ToneShift | Rewrites any message into the exact tone you pick, shown side by side. |
| Alib-AI | Excuse generator that remembers what you told whom, so you never repeat one. |
| Project | One-liner |
|---|---|
| MoodyReads | Recommends books that match your current mood and reading taste. |
| Moodiflix | Recommends movies and shows tuned to how you're feeling. |
| Project | One-liner |
|---|---|
| My-AI-Things | ML notebooks — exploratory data analysis, TF-IDF/NLP, and scikit-learn. |
| Noise-Reduction | Audio denoising via spectral-gating signal processing (NumPy/SciPy). |
| LeetCode-Problems | Curated, solved LeetCode problems for algorithms and data structures. |
| Coding-practice | Coding exercises and interview prep across core CS fundamentals. |
- 🛠️ Hardware Engineer at Cisco — VLSI, RTL design, and verification
- 🔁 Ship a new hardware design every day across four daily-build portfolios (35+ and counting)
- 🌙 Build and launch AI apps as a relentless side pursuit — 20+ products shipped
- 🎓 M.S. in Computer Engineering, NC State University
- 💡 Driven by practical AI, product experimentation, and systems that solve everyday problems
