Computer Architecture – Verilog Circuit Design Project

Digital circuit design project for a Computer Architecture course using Verilog, unit testbenches, and waveform verification with GTKWave.

Project Overview

This repository contains the implementation of basic combinational logic circuits and a 4-bit arithmetic shift circuit developed in Verilog. Each module is tested using a dedicated unit testbench, and VCD waveforms are generated for debugging and verification.

Key concepts covered:

• Verilog module design (combinational logic)
• Two’s complement representation
• Arithmetic shifting and sign-extension
• Testbench development
• Waveform debugging using VCD + GTKWave
• Build automation using Make

Implemented Circuits (Step-1)

1-bit Logic Gates

• NOT gate
• NAND gate
• NOR gate

4-bit Arithmetic Shift Circuit

• 4-bit input
• 4-bit output
• Shift amount: 1
• Direction chosen: Arithmetic Right Shift
• Includes sign-extension (MSB preserved)

Implemented Circuits (Step-2)

4-bit Logic Gates

• AND
• NAND
• OR
• NOR
• XOR
• XNOR
• NOT

4-bit Arithmetic Circuits

• Adder: 4-bit adder with carry-in and carry-out.
• Subtractor: 4-bit subtractor with borrow-out.
• Multiplier: 4-bit multiplier with an 8-bit result.
• Divider: 4-bit divider that produces a 4-bit quotient and a 4-bit remainder.

4-bit Barrel Shifter

A 2x4-bit input barrel shifter with a 2-bit select line to control the operation:

• 00: No-op (output = input)
• 01: Logical Shift Left by 1
• 10: Logical Shift Right by 1
• 11: Arithmetic Shift Right by 1 (with sign extension)

Folder Structure

.
├── step-1/
│   ├── verilog/
│   ├── tests/
│   ├── waves/
│   └── Makefile
└── step-2/
    ├── verilog/
    │   ├── arithmetic/
    │   │   ├── add4.v
    │   │   ├── sub4.v
    │   │   ├── mul4.v
    │   │   └── div4.v
    │   ├── gates_step2.v
    │   └── ashifter_step2.v
    ├── tests/
    │   ├── arithmetic/
    │   │   ├── tb_add4.v
    │   │   ├── tb_sub4.v
    │   │   ├── tb_mul4.v
    │   │   └── tb_div4.v
    │   ├── tb_and4.v
    │   ├── tb_nand4.v
    │   │   ... (and so on for all gates)
    │   └── tb_ashifter_step2.v
    ├── waves/
    │   ├── add4.vcd
    │   ├── sub4.vcd
    │   │   ... (and so on for all modules)
    └── Makefile

How to Run

Commands should be run from the root of the project directory.

Step-1 Tests

# Run all tests for Step-1
make -C step-1
Open waveforms for Step-1

make -C step-1 wave_not
make -C step-1 wave_nand
make -C step-1 wave_nor
make -C step-1 wave_shift
Clean generated files for Step-1

make -C step-1 clean

Step-2 Tests

# Run all tests for Step-2
make -C step-2
Open waveforms for Step-2

make -C step-2 wave_gates
make -C step-2 wave_arithmetic
make -C step-2 wave_shifter
Clean generated files for Step-2

make -C step-2 clean

Example: Arithmetic Right Shift Behavior

Arithmetic right shift preserves the sign bit (MSB) for signed numbers (two’s complement). For example:

A = 1000
Y = 1100

The MSB remains 1 due to sign-extension, maintaining correct signed behavior.

Tools Used

• Icarus Verilog (iverilog + vvp)
• GTKWave (waveform viewer)
• Make (build automation)
• LaTeX (report preparation, optional/extra credit depending on course)

Next Steps

Future stages of this project expand into a full ALU implementation including logic operations, arithmetic operations (add/sub/mul/div), a control module with opcodes, and extended bit-width options (8/16/32-bit).