Updated to use new cocotb runners

pyproject.toml

@@ -28,7 +28,7 @@ requires-python = ">= 3.9"
 license = "Apache-2.0"
 license-files = ["LICENSE"]
 dependencies = [
-    "siliconcompiler >= 0.36.5",
+    "siliconcompiler >= 0.38.0",
     "lambdalib >= 0.12.0, <0.14.0"
 ]
 dynamic = ["version"]
@@ -39,7 +39,7 @@ test = [
     "pytest-xdist == 3.8.0",
     "pytest-timeout == 2.4.0",
     "flake8 == 7.3.0",
-    "switchboard-hw==0.3.3",
+    "switchboard-hw==0.3.4",
     "cocotb==2.0.1",
     "cocotb-bus==0.3.0",
     "cocotbext-axi==0.1.28",

tests/adapters/axi2umi/test_axi2umi.py

@@ -3,7 +3,8 @@
 
 import pytest
 
-from siliconcompiler import Design
+from siliconcompiler import Sim
+from siliconcompiler.targets.dvflow_cocotb import dvflow_cocotb
 
 import cocotb
 from cocotb.clock import Clock
@@ -21,6 +22,8 @@
 
 from umi.adapters.axi2umi.axi2umi import AXI2UMI
 
+from cocotb_utils import CocotbSimEnv
+
 
 class Env:
     """Reusable test environment for AXI4 Full to UMI adapter tests."""
@@ -346,32 +349,31 @@ async def drop_test(dut, test_n_transactions=10, resp_valid_gen=None):
     await ClockCycles(dut.clk, 10)
 
 
-class TbDesign(Design):
+class TbDesign(CocotbSimEnv):
 
     def __init__(self):
-        super().__init__()
-
-        # Set the design's name
-        self.set_name("tb_axi2umi")
-
-        # Establish the root directory for all design-related files
-        self.set_dataroot("tb_axi2umi", __file__)
-
-        # Configure filesets within the established data root
-        with self.active_dataroot("tb_axi2umi"):
-            with self.active_fileset("testbench.cocotb"):
-                self.set_topmodule("axi2umi")
-                self.add_file("test_axi2umi.py", filetype="python")
-                self.add_depfileset(AXI2UMI(), "rtl")
+        super().__init__(
+            name="tb_axi2umi",
+            topmodule="axi2umi",
+            files=[__file__],
+            dep=[AXI2UMI()]
+        )
 
 
 @pytest.mark.cocotb
 @pytest.mark.parametrize("simulator", ["icarus", "verilator"])
 def test_axi2umi(simulator):
-    from run_cocotb_sim import load_cocotb_test
-    load_cocotb_test(
-        design=TbDesign(),
-        simulator=simulator,
+    project = Sim(TbDesign())
+    project.add_fileset("testbench.cocotb")
+
+    dvflow_cocotb(
+        project=project,
         trace=False,
+        timescale=("1ns", "1ps"),
         seed=None
     )
+
+    project.set_flow(f"{simulator}cocotbdvflow")
+
+    project.run()
+    project.summary()

tests/adapters/axi2umi/test_axird2umi.py

@@ -3,7 +3,8 @@
 
 import pytest
 
-from siliconcompiler import Design
+from siliconcompiler import Sim
+from siliconcompiler.targets.dvflow_cocotb import dvflow_cocotb
 
 import cocotb
 from cocotb.clock import Clock
@@ -20,6 +21,8 @@
 
 from umi.adapters.axi2umi.axi2umi import AXI2UMI
 
+from cocotb_utils import CocotbSimEnv
+
 
 class Env:
     """Reusable test environment for AXI4 Full Read to UMI adapter tests."""
@@ -150,32 +153,31 @@ async def basic_test(
     await ClockCycles(dut.clk, 10)
 
 
-class TbDesign(Design):
+class TbDesign(CocotbSimEnv):
 
     def __init__(self):
-        super().__init__()
-
-        # Set the design's name
-        self.set_name("tb_axird2umi")
-
-        # Establish the root directory for all design-related files
-        self.set_dataroot("tb_axird2umi", __file__)
-
-        # Configure filesets within the established data root
-        with self.active_dataroot("tb_axird2umi"):
-            with self.active_fileset("testbench.cocotb"):
-                self.set_topmodule("axird2umi")
-                self.add_file("test_axird2umi.py", filetype="python")
-                self.add_depfileset(AXI2UMI(), "rtl")
+        super().__init__(
+            name="tb_axird2umi",
+            topmodule="axird2umi",
+            files=[__file__],
+            dep=[AXI2UMI()]
+        )
 
 
 @pytest.mark.cocotb
 @pytest.mark.parametrize("simulator", ["icarus", "verilator"])
 def test_axird2umi(simulator):
-    from run_cocotb_sim import load_cocotb_test
-    load_cocotb_test(
-        design=TbDesign(),
-        simulator=simulator,
+    project = Sim(TbDesign())
+    project.add_fileset("testbench.cocotb")
+
+    dvflow_cocotb(
+        project=project,
         trace=False,
+        timescale=("1ns", "1ps"),
         seed=None
     )
+
+    project.set_flow(f"{simulator}cocotbdvflow")
+
+    project.run()
+    project.summary()

tests/adapters/axi2umi/test_axiwr2umi.py

@@ -4,7 +4,8 @@
 
 import pytest
 
-from siliconcompiler import Design
+from siliconcompiler import Sim
+from siliconcompiler.targets.dvflow_cocotb import dvflow_cocotb
 
 import cocotb
 from cocotb.clock import Clock
@@ -22,6 +23,8 @@
 
 from umi.adapters.axi2umi.axi2umi import AXI2UMI
 
+from cocotb_utils import CocotbSimEnv
+
 
 class ErrorInjectingUmiMemoryDevice(UmiMemoryDevice):
     """
@@ -370,32 +373,31 @@ async def error_injection_test(
     await ClockCycles(dut.clk, 10)
 
 
-class TbDesign(Design):
+class TbDesign(CocotbSimEnv):
 
     def __init__(self):
-        super().__init__()
-
-        # Set the design's name
-        self.set_name("tb_axiwr2umi")
-
-        # Establish the root directory for all design-related files
-        self.set_dataroot("tb_axiwr2umi", __file__)
-
-        # Configure filesets within the established data root
-        with self.active_dataroot("tb_axiwr2umi"):
-            with self.active_fileset("testbench.cocotb"):
-                self.set_topmodule("axiwr2umi")
-                self.add_file("test_axiwr2umi.py", filetype="python")
-                self.add_depfileset(AXI2UMI(), "rtl")
+        super().__init__(
+            name="tb_axiwr2umi",
+            topmodule="axiwr2umi",
+            files=[__file__],
+            dep=[AXI2UMI()]
+        )
 
 
 @pytest.mark.cocotb
 @pytest.mark.parametrize("simulator", ["icarus", "verilator"])
 def test_axiwr2umi(simulator):
-    from run_cocotb_sim import load_cocotb_test
-    load_cocotb_test(
-        design=TbDesign(),
-        simulator=simulator,
+    project = Sim(TbDesign())
+    project.add_fileset("testbench.cocotb")
+
+    dvflow_cocotb(
+        project=project,
         trace=False,
+        timescale=("1ns", "1ps"),
         seed=None
     )
+
+    project.set_flow(f"{simulator}cocotbdvflow")
+
+    project.run()
+    project.summary()

tests/adapters/tl2umi/test_advanced.py

@@ -3,8 +3,12 @@
 from cocotb.handle import SimHandleBase
 from cocotb.triggers import ClockCycles
 
-from tl_driver import TLTransaction, TLArithParam, TLLogicParam
-from tl2umi_env import TL2UMIEnv, create_expected_write_response, create_expected_read_response
+from adapters.tl2umi.tl_driver import TLTransaction, TLArithParam, TLLogicParam
+from adapters.tl2umi.tl2umi_env import (
+    TL2UMIEnv,
+    create_expected_write_response,
+    create_expected_read_response
+)
 
 
 @cocotb.test(timeout_time=50, timeout_unit="ms")

tests/adapters/tl2umi/test_basic.py

@@ -2,8 +2,12 @@
 
 from cocotb.handle import SimHandleBase
 
-from tl_driver import TLTransaction
-from tl2umi_env import TL2UMIEnv, create_expected_write_response, create_expected_read_response
+from adapters.tl2umi.tl_driver import TLTransaction
+from adapters.tl2umi.tl2umi_env import (
+    TL2UMIEnv,
+    create_expected_write_response,
+    create_expected_read_response
+)
 
 
 @cocotb.test(timeout_time=50, timeout_unit="ms")

tests/adapters/tl2umi/test_tl2umi_run.py

@@ -2,47 +2,48 @@
 
 import pytest
 
-from siliconcompiler import Design
+from siliconcompiler import Sim
+from siliconcompiler.targets.dvflow_cocotb import dvflow_cocotb
 
 from umi.adapters import TL2UMI
 
+from cocotb_utils import CocotbSimEnv
 
-class TL2UMITestbench(Design):
+
+class TL2UMITestbench(CocotbSimEnv):
     """TL2UMI testbench for cocotb testing (UMI memory agent in Python)"""
 
     def __init__(self, aw=64, dw=64):
-        super().__init__()
-
-        self.set_name(f"tb_tl2umi_aw{aw}_dw{dw}")
-        self.set_dataroot("tl2umi", __file__)
-
-        with self.active_dataroot("tl2umi"):
-            with self.active_fileset("testbench.cocotb"):
-                self.set_topmodule("tl2umi")
-                self.set_param("AW", str(aw))
-                self.set_param("DW", str(dw))
-                # Add test files
-                self.add_file("test_basic.py", filetype="python")
-                self.add_file("test_advanced.py", filetype="python")
-                # Add helper Python modules (populates PYTHONPATH via DVFlow)
-                self.add_file("tl2umi_env.py", filetype="python")
-                self.add_file("tl_driver.py", filetype="python")
-                self.add_file("tl_monitor.py", filetype="python")
-                # Add RTL dependency (no Verilog wrapper needed)
-                self.add_depfileset(TL2UMI(), "rtl")
+        super().__init__(
+            name=f"tb_tl2umi_aw{aw}_dw{dw}",
+            topmodule="tl2umi",
+            files=[
+                "adapters/tl2umi/test_basic.py",
+                "adapters/tl2umi/test_advanced.py",
+            ],
+            dep=[TL2UMI()],
+            param=[("AW", str(aw)), ("DW", str(dw))]
+        )
 
 
 @pytest.mark.cocotb
 @pytest.mark.parametrize("simulator, aw, dw", list(itertools.product(
     ["verilator"],
-    [32, 64],
+    [64],
     [64, 128]
 )))
 def test_tl2umi(simulator, aw, dw):
-    from run_cocotb_sim import load_cocotb_test
-    load_cocotb_test(
-        design=TL2UMITestbench(aw=aw, dw=dw),
-        simulator=simulator,
+    project = Sim(TL2UMITestbench(aw=aw, dw=dw))
+    project.add_fileset("testbench.cocotb")
+
+    dvflow_cocotb(
+        project=project,
         trace=False,
+        timescale=("1ns", "1ps"),
         seed=None
     )
+
+    project.set_flow(f"{simulator}cocotbdvflow")
+
+    project.run()
+    project.summary()

tests/adapters/tl2umi/tl2umi_env.py

@@ -5,26 +5,18 @@
 # the Verilog umi_memagent. The DUT is tl2umi directly (no wrapper needed).
 
 from cocotb.clock import Clock
-from cocotb.triggers import ClockCycles, Timer
+from cocotb.triggers import ClockCycles
 
 from cocotb_bus.scoreboard import Scoreboard
 
 from cocotbext.umi.drivers.sumi_driver import SumiDriver
 from cocotbext.umi.monitors.sumi_monitor import SumiMonitor
 from cocotbext.umi.models.umi_memory_device import UmiMemoryDevice
 
-from tl_driver import TLDriver
-from tl_monitor import TLMonitor, TLDResponse, TLDOpcode
+from adapters.tl2umi.tl_driver import TLDriver
+from adapters.tl2umi.tl_monitor import TLMonitor, TLDResponse, TLDOpcode
 
-
-async def do_reset(reset, time_ns, active_level=False):
-    """Perform an async reset"""
-    reset.value = not active_level
-    await Timer(1, unit="step")
-    reset.value = active_level
-    await Timer(time_ns, "ns")
-    reset.value = not active_level
-    await Timer(1, unit="step")
+from cocotb_utils import drive_reset
 
 
 class TL2UMIEnv:
@@ -97,7 +89,7 @@ def _build(self):
     async def start(self):
         """Start clocks and perform reset"""
         Clock(self.clk, self.clk_period_ns, unit="ns").start()
-        await do_reset(self.nreset, self.clk_period_ns)
+        await drive_reset(self.nreset, self.clk_period_ns)
 
         # Initialize DUT configuration signals
         self.dut.srcaddr.value = 0xAE510000