Moving large benchmarks into separate group

README.md

@@ -16,7 +16,7 @@ LogikBench is a curated open source RTL benchmark suite that enables reproducibl
 
 | Challenge              | LogikBench Solution                                     |
 |------------------------|---------------------------------------------------------|
-| No "Spec CPU for RTL"  | 220 standardized RTL benchmark circuits                 |
+| No "Spec CPU for RTL"  | 239 standardized RTL benchmark circuits                 |
 | Circuit diversity      | Broad mix of circuit types, sizes, and source origins   |
 | Size diversity         | Per-circuit parameterization across multiple scales     |
 | Trust                  | Documented source code provenance and curation criteria |
@@ -27,11 +27,12 @@ LogikBench is a curated open source RTL benchmark suite that enables reproducibl
 
 LogikBench includes the following benchmark types:
 
-| Benchmark type               | Groups (-g)               |
-|------------------------------|---------------------------|
-| Micro-benchmarks             | basic, arithmetic         |
-| Legacy synthetic benchmarks  | epfl, isca85, isca89      |
-| Very large and real circuits | blocks                    |
+| Benchmark type                  | Groups (-g)                 |
+|---------------------------------|-----------------------------|
+| Micro-benchmarks                | basic, arithmetic           |
+| Legacy synthetic benchmarks     | epfl, isca85, isca89, koios |
+| Divers catalog of real circuits | blocks                      |
+| Very large benchmarks           | large                       |
 
 🏆 [Results dashboard](https://zeroasiccorp.github.io/logikbench)
 
@@ -570,20 +571,15 @@ lb lint -g basic
 | regfile | Register file | [readme](logikbench/benchmarks/memory/regfile/README.md) |  |
 | rom | Read-only memory | [rom.v](logikbench/benchmarks/memory/rom/rtl/rom.v) |  |
 
-### Complex Blocks (48 benchmarks)
+### Complex Blocks (37 benchmarks)
 
 | Benchmark | Description | Source | AI |
 |-----------|-------------|--------|----|
-| aes | AES encryption core | [readme](logikbench/benchmarks/blocks/aes/README.md) |  |
 | apbregs | APB register file | [apbregs.v](logikbench/benchmarks/blocks/apbregs/rtl/apbregs.v) |  |
-| axicrossbar | AXI crossbar | [readme](logikbench/benchmarks/blocks/axicrossbar/README.md) |  |
 | axiram | AXI RAM interface | [readme](logikbench/benchmarks/blocks/axiram/README.md) |  |
-| blackparrot | BlackParrot RISC-V core | [readme](logikbench/benchmarks/blocks/blackparrot/README.md) |  |
 | conv2d | Streaming 3x3 2D convolution | [readme](logikbench/benchmarks/blocks/conv2d/README.md) | Y |
-| coralnpu | CoralNPU neural accelerator | [readme](logikbench/benchmarks/blocks/coralnpu/README.md) |  |
 | crc32 | CRC-32 generator | [readme](logikbench/benchmarks/blocks/crc32/README.md) | Y |
 | codec8b10b | 8b/10b line encoder/decoder | [readme](logikbench/benchmarks/blocks/codec8b10b/README.md) | Y |
-| cva6 | CVA6 (Ariane) RISC-V core | [readme](logikbench/benchmarks/blocks/cva6/README.md) |  |
 | ddc | Digital down-converter (NCO/mixer/CIC/FIR) | [readme](logikbench/benchmarks/blocks/ddc/README.md) | Y |
 | ethmac | Ethernet MAC | [readme](logikbench/benchmarks/blocks/ethmac/README.md) |  |
 | fft | Fast Fourier Transform | [readme](logikbench/benchmarks/blocks/fft/README.md) | Y |
@@ -601,14 +597,10 @@ lb lint -g basic
 | lfsr | Linear feedback shift register | [readme](logikbench/benchmarks/blocks/lfsr/README.md) |  |
 | linkmap | JESD204-style transport framer/deframer | [readme](logikbench/benchmarks/blocks/linkmap/README.md) | Y |
 | lpddr5 | LPDDR5 memory controller (UMI + DFI, ECC) | [readme](logikbench/benchmarks/blocks/lpddr5/README.md) | Y |
-| lz77 | LZ77 (LZSS) compressor/decompressor | [readme](logikbench/benchmarks/blocks/lz77/README.md) | Y |
 | median3x3 | Streaming 3x3 median filter | [readme](logikbench/benchmarks/blocks/median3x3/README.md) | Y |
-| nvdla | NVDLA deep-learning accelerator | [readme](logikbench/benchmarks/blocks/nvdla/README.md) |  |
-| ofdm | OFDM modem (QAM + IFFT/FFT) | [readme](logikbench/benchmarks/blocks/ofdm/README.md) | Y |
 | openpiton | OpenPiton manycore tile | [readme](logikbench/benchmarks/blocks/openpiton/README.md) |  |
 | picorv32 | PicoRV32 RISC-V core | [readme](logikbench/benchmarks/blocks/picorv32/README.md) |  |
 | reedsolomon | Reed-Solomon RS(544,514) codec | [readme](logikbench/benchmarks/blocks/reedsolomon/README.md) | Y |
-| rocket | Rocket RISC-V core | [readme](logikbench/benchmarks/blocks/rocket/README.md) |  |
 | sad8x8 | 8x8 sum of absolute differences | [readme](logikbench/benchmarks/blocks/sad8x8/README.md) | Y |
 | serv | SERV bit-serial RISC-V core | [readme](logikbench/benchmarks/blocks/serv/README.md) |  |
 | sobel3x3 | Streaming 3x3 Sobel edge detector | [readme](logikbench/benchmarks/blocks/sobel3x3/README.md) | Y |
@@ -619,10 +611,24 @@ lb lint -g basic
 | umidev | UMI device endpoint | [readme](logikbench/benchmarks/blocks/umidev/README.md) |  |
 | umiregs | UMI register file | [umiregs.v](logikbench/benchmarks/blocks/umiregs/rtl/umiregs.v) |  |
 | viterbi | Viterbi decoder | [readme](logikbench/benchmarks/blocks/viterbi/README.md) | Y |
-| vortex | Vortex GPU core | [readme](logikbench/benchmarks/blocks/vortex/README.md) |  |
-| wally | CVW-Wally RISC-V core | [wally/](logikbench/benchmarks/blocks/wally/) |  |
 | wordalign | Comma detect + bitslip aligner | [readme](logikbench/benchmarks/blocks/wordalign/README.md) | Y |
 
+### Large Benchmarks (11 benchmarks)
+
+| Benchmark | Description | Source | AI |
+|-----------|-------------|--------|----|
+| aes | AES encryption core | [readme](logikbench/benchmarks/large/aes/README.md) |  |
+| axicrossbar | AXI crossbar | [readme](logikbench/benchmarks/large/axicrossbar/README.md) |  |
+| blackparrot | BlackParrot RISC-V core | [readme](logikbench/benchmarks/large/blackparrot/README.md) |  |
+| coralnpu | CoralNPU neural accelerator | [readme](logikbench/benchmarks/large/coralnpu/README.md) |  |
+| cva6 | CVA6 (Ariane) RISC-V core | [readme](logikbench/benchmarks/large/cva6/README.md) |  |
+| lz77 | LZ77 compressor/decompressor | [readme](logikbench/benchmarks/large/lz77/README.md) | Y |
+| nvdla | NVDLA deep-learning accelerator | [readme](logikbench/benchmarks/large/nvdla/README.md) |  |
+| ofdm | OFDM modem (QAM + IFFT/FFT) | [readme](logikbench/benchmarks/large/ofdm/README.md) | Y |
+| rocket | Rocket RISC-V core | [readme](logikbench/benchmarks/large/rocket/README.md) |  |
+| vortex | Vortex GPU core | [readme](logikbench/benchmarks/large/vortex/README.md) |  |
+| wally | CVW-Wally RISC-V core | [readme](logikbench/benchmarks/large/wally/README.md) |  |
+
 ### EPFL Benchmarks (19 benchmarks)
 
 | Benchmark | Description | Source |
@@ -715,25 +721,22 @@ Deep-learning accelerator and layer designs (pure RTL, hard blocks disabled). Se
 | softmax | Softmax classification layer | [softmax.v](logikbench/benchmarks/koios/softmax/rtl/softmax.v) |
 | spmv | Sparse matrix-vector multiplication | [spmv.v](logikbench/benchmarks/koios/spmv/rtl/spmv.v) |
 | lstm | LSTM engine | [lstm.v](logikbench/benchmarks/koios/lstm/rtl/lstm.v) |
-| robot_rl | Reinforcement-learning robot / maze application | [robot_rl.v](logikbench/benchmarks/koios/robot_rl/rtl/robot_rl.v) |
+| robot_rl | Reinforcement-learning | [robot_rl.v](logikbench/benchmarks/koios/robot_rl/rtl/robot_rl.v) |
 | dnnweaver | DNNWeaver-like accelerator | [dnnweaver.v](logikbench/benchmarks/koios/dnnweaver/rtl/dnnweaver.v) |
-| tpu_like_small_os | Google-TPU-v1-like accelerator (small, output-stationary) | [tpu_like_small_os.v](logikbench/benchmarks/koios/tpu_like_small_os/rtl/tpu_like_small_os.v) |
-| tpu_like_small_ws | Google-TPU-v1-like accelerator (small, weight-stationary) | [tpu_like_small_ws.v](logikbench/benchmarks/koios/tpu_like_small_ws/rtl/tpu_like_small_ws.v) |
+| tpu_like_small_os | Google-TPU-v1 (output-stationary) | [tpu_like_small_os.v](logikbench/benchmarks/koios/tpu_like_small_os/rtl/tpu_like_small_os.v) |
+| tpu_like_small_ws | Google-TPU-v1 (weight-stationary) | [tpu_like_small_ws.v](logikbench/benchmarks/koios/tpu_like_small_ws/rtl/tpu_like_small_ws.v) |
 | clstm_like_small | CLSTM-like accelerator (small) | [clstm_like_small.v](logikbench/benchmarks/koios/clstm_like_small/rtl/clstm_like_small.v) |
 | clstm_like_medium | CLSTM-like accelerator (medium) | [clstm_like_medium.v](logikbench/benchmarks/koios/clstm_like_medium/rtl/clstm_like_medium.v) |
 | dla_like_small | Intel-DLA-like accelerator (small) | [dla_like_small.v](logikbench/benchmarks/koios/dla_like_small/rtl/dla_like_small.v) |
 | dla_like_medium | Intel-DLA-like accelerator (medium) | [dla_like_medium.v](logikbench/benchmarks/koios/dla_like_medium/rtl/dla_like_medium.v) |
-| bwave_like_fixed_small | Microsoft-Brainwave-like NPU (fixed-point, small) | [bwave_like_fixed_small.v](logikbench/benchmarks/koios/bwave_like_fixed_small/rtl/bwave_like_fixed_small.v) |
-| bwave_like_float_small | Microsoft-Brainwave-like NPU (floating-point, small) | [bwave_like_float_small.v](logikbench/benchmarks/koios/bwave_like_float_small/rtl/bwave_like_float_small.v) |
+| bwave_like_fixed_small | Microsoft-Brainwave-like NPU | [bwave_like_fixed_small.v](logikbench/benchmarks/koios/bwave_like_fixed_small/rtl/bwave_like_fixed_small.v) |
+| bwave_like_float_small | Microsoft-Brainwave-like NPU | [bwave_like_float_small.v](logikbench/benchmarks/koios/bwave_like_float_small/rtl/bwave_like_float_small.v) |
 
 ----
 
 
-
 ## Leaderboard (WIP)
 
-
-
 Targets ranked by total LUTs over all benchmarks (config: `small`), lowest first. A benchmark with no result for a target is charged the highest LUT count any target reached on it.
 Comparing different FPGA architectures is by definition an apples to oranges exercise. Ranking by no means implies quality or goodness, it's just a neat way to compress and order data.
 

logikbench/__init__.py

@@ -10,6 +10,7 @@
 from logikbench.benchmarks import arithmetic
 from logikbench.benchmarks import memory
 from logikbench.benchmarks import blocks
+from logikbench.benchmarks import large
 from logikbench.benchmarks import epfl
 from logikbench.benchmarks import iscas85
 from logikbench.benchmarks import iscas89
@@ -20,6 +21,7 @@
     "arithmetic",
     "memory",
     "blocks",
+    "large",
     "epfl",
     "iscas85",
     "iscas89",

logikbench/apps/lb.py

@@ -21,7 +21,7 @@
 SCHEMA_VERSION = 1
 
 # benchmark groups available to both subcommands
-ALL_GROUPS = ['basic', 'memory', 'arithmetic', 'epfl', 'blocks',
+ALL_GROUPS = ['basic', 'memory', 'arithmetic', 'epfl', 'blocks', 'large',
               'iscas85', 'iscas89', 'koios']
 
 # metrics tracked are determined by the run mode (fpga vs asic synthesis)

logikbench/benchmarks/blocks/README.md

@@ -8,9 +8,7 @@ Each benchmark circuit includes information about the author, license, and sourc
 
 | Circuit       | Params      | Ready  | Description     |
 |---------------|-------------|--------|-----------------|
-| aes           | n/a         | Y      | 128b AES cipher
 | apbregs       | DW,AW       | Y      | APB register file
-| axicrossbar   | DW,AW,NM,NS | Y      | AXI crossbar
 | axidev        | DW,AW       |        | AXI device
 | axihost       | DW,AW       |        | AXI host
 | conv2d        | DW, N       |        | 2D convolution filter
@@ -28,7 +26,6 @@ Each benchmark circuit includes information about the author, license, and sourc
 | lfsr          | DW,LFSRW    | Y      | Configurable LFSR
 | matmul        | DW          |        | Systolic array matmul
 | median3x3     | DW          |        | 2D median filter
-| ofdm          |             |        |
 | picorv32      |             | Y      | 32b RISC-V CPU
 | sad8x8        | DW          |        | 2D SAD filter
 | serv          |             | Y      | Bit serial CPU

logikbench/benchmarks/blocks/__init__.py

@@ -1,11 +1,6 @@
-from .aes.aes import Aes
 from .apbregs.apbregs import Apbregs
-from .axicrossbar.axicrossbar import Axicrossbar
 from .axiram.axiram import Axiram
-from .blackparrot.blackparrot import BlackParrot
-from .coralnpu.coralnpu import CoralNPU
 from .crc32.crc32 import Crc32
-from .cva6.cva6 import Cva6
 from .ddc.ddc import Ddc
 from .ethmac.ethmac import Ethmac
 from .fft.fft import Fft
@@ -20,13 +15,9 @@
 from .i2c.i2c import I2c
 from .lfsr.lfsr import Lfsr
 from .lpddr5.lpddr5 import Lpddr5
-from .lz77.lz77 import Lz77
-from .nvdla.nvdla import Nvdla
-from .ofdm.ofdm import Ofdm
 from .openpiton.openpiton import Openpiton
 from .picorv32.picorv32 import Picorv32
 from .reedsolomon.reedsolomon import Reedsolomon
-from .rocket.rocket import Rocket
 from .spi.spi import Spi
 from .serv.serv import Serv
 from .tpu.tpu import Tpu
@@ -35,8 +26,6 @@
 from .umidev.umidev import Umidev
 from .umiregs.umiregs import Umiregs
 from .viterbi.viterbi import Viterbi
-from .vortex.vortex import Vortex
-from .wally.wally import Wally
 
 from .conv2d.conv2d import Conv2d
 from .codec8b10b.codec8b10b import Codec8b10b
@@ -49,14 +38,9 @@
 from .sobel3x3.sobel3x3 import Sobel3x3
 
 __all__ = [
-    "Aes",
     "Apbregs",
-    "Axicrossbar",
     "Axiram",
-    "BlackParrot",
-    "CoralNPU",
     "Crc32",
-    "Cva6",
     "Ddc",
     "Ethmac",
     "Fft",
@@ -71,13 +55,9 @@
     "I2c",
     "Lfsr",
     "Lpddr5",
-    "Lz77",
-    "Nvdla",
-    "Ofdm",
     "Openpiton",
     "Picorv32",
     "Reedsolomon",
-    "Rocket",
     "Spi",
     "Serv",
     "Tpu",
@@ -86,8 +66,6 @@
     "Umidev",
     "Umiregs",
     "Viterbi",
-    "Vortex",
-    "Wally",
     "Conv2d",
     "Codec8b10b",
     "Gearbox66",

logikbench/benchmarks/blocks/umicross/README.md

@@ -8,9 +8,10 @@ UMI crossbar (`umi_crossbar`) from Zero ASIC's UMI library, configured as an
 - repo: https://github.com/zeroasiccorp/umi (PyPI package `umi`)
 - module: `umi.sumi.Crossbar` (topmodule `umi_crossbar`)
 
-No RTL is vendored: the source is referenced from the installed `umi` pip
-package (resolved at import). The Vmux (lambdalib) and umi Arbiter dependency
-filesets are pulled from their packages.
+The umi RTL is vendored in `rtl/` (`umi_crossbar`, `umi_arbiter`, plus the
+`umi_messages.vh` header), copied from the `umi` pip package (version 0.4.15).
+`Vmux` (lambdalib) remains a dependency -- it is a mux-shim library, not
+benchmark RTL. Logic is unchanged; configured via the parameters below.
 
 # Parameters (overridden in umicross.py)
 

logikbench/benchmarks/blocks/umicross/rtl/umi_arbiter.v

@@ -0,0 +1,99 @@
+/*******************************************************************************
+ * Copyright 2020 Zero ASIC Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----
+ *
+ * Documentation:
+ * - Dynamically configurable arbiter (fixed, roundrobin, reserve,...)
+ *
+ ******************************************************************************/
+
+module umi_arbiter #(parameter N = 4,    // number of inputs
+                     parameter PROP = "" // cell selector
+                     )
+   (// controls
+    input          clk,
+    input          nreset,
+    input [1:0]    mode,     // [00]=priority,[01]=roundrobin,[1x]=reserved
+    input [N-1:0]  mask,     // 1 = disable request, 0 = enable request
+    input [N-1:0]  requests, // incoming requests
+    output [N-1:0] grants    // outgoing grants
+    );
+
+   wire                collision;
+   reg [N-1:0]         thermometer;
+   wire [N-1:0]        spec_requests;
+   wire [N-1:0]        block;
+   genvar              i,j;
+
+   // NOTE: The thermometer mask works correctly in case of a collision
+   // that is followed by a single request from a masked source.
+   // Consider, 4 requestors but only 0 and 1 are requesting:
+   // cycle 0: req[0] = 1, req[1] = 1, grants[0] = 1, grants[1] = 0, collision = 1, therm = 4'b0000
+   // cycle 1: req[0] = 0, req[1] = 1, grants[0] = 0, grants[1] = 1, collision = 0, therm = 4'b0001
+   // cycle 2: req[0] = 1, req[1] = 0, grants[0] = 0, grants[1] = 0, collision = 1, therm = 4'b0001
+   // cycle 3: req[0] = 1, req[1] = 0, grants[0] = 0, grants[1] = 0, collision = 1, therm = 4'b0011
+   // cycle 4: req[0] = 1, req[1] = 0, grants[0] = 0, grants[1] = 0, collision = 1, therm = 4'b0111
+   // cycle 5: req[0] = 1, req[1] = 0, grants[0] = 1, grants[1] = 0, collision = 0, therm = 4'b0000
+   // Here, after cycle 0, requestor 0 was masked due to a collision with
+   // requestor 1. When requestor 0 sends its second request with no other
+   // requestors trying, it incurs a 3 cycle penalty for the thermometer to
+   // fill up. While the 3 cycle penalty is detrimental to performance the
+   // system does not hang.
+
+   // Thermometer mask that gets hotter with every collision
+   // wraps to zero when all ones
+   generate if (N > 1)
+     begin
+        always @ (posedge clk or negedge nreset)
+          if (~nreset)
+            thermometer[N-1:0] <= {N{1'b0}};
+          else if(collision & (mode[1:0]==2'b10))
+            thermometer[N-1:0] <= (&thermometer[N-2:0]) ? {N{1'b0}} : {thermometer[N-2:0],1'b1};
+     end
+   else
+     begin
+        always @ (posedge clk or negedge nreset)
+          if (~nreset)
+            thermometer[N-1:0] <= {N{1'b0}};
+          else
+            thermometer[N-1:0] <= {N{1'b0}};
+     end
+   endgenerate
+
+   // 1. Create N rotated set of requests
+   // 2. Feed requests into fixed priority encoders
+   // double width needed for rotation
+   assign spec_requests = ~mask[N-1:0] &
+                          ~thermometer[N-1:0] &
+                           requests[N-1:0];
+
+   // Priority block
+   assign block[0] = 1'b0;
+   for (j=N-1; j>=1; j=j-1)
+     begin : ipri
+        assign block[j] = |spec_requests[j-1:0];
+     end
+
+   assign grants[N-1:0] = spec_requests[N-1:0] & ~block[N-1:0];
+
+   // Detect collision on pushback
+   assign collision = |(requests[N-1:0] & ~grants[N-1:0]);
+
+`ifdef VERILATOR
+   assert property (@(posedge clk) $onehot0(grants));
+`endif
+
+endmodule