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  1. Jia_hao-risc-v-CPU-v1.0 Jia_hao-risc-v-CPU-v1.0 Public

    A simple risc-v single-core CPU design written in Verilog, developed for learning and practicing computer architecture and hardware description languages.

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  2. jia_hao-risc-v-CPU-pipeline jia_hao-risc-v-CPU-pipeline Public

    Jia_hao-risc-v-CPU v2.2: Upgrading from single-cycle to a 7-stage pipelined architecture with full data & control hazard resolution.

    Verilog 1

  3. jia_xin-risc-v-soc jia_xin-risc-v-soc Public

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