Axiom CVA6

Runs the CVA6 RISC-V core as a real gem5 BaseCPU via axiom (AXION), a gem5 extension that bridges gem5 SimObjects to RTL blocks simulated by Verilator over a pin-level AXI4 interface.

CVA6RTLCpu (src/cva6/) is a concrete leaf on top of axiom's abstract RTLBaseCpu: it wraps a Verilated cva6_top module (CVA6 core + axi_riscv_atomics adapter, flattened onto axiom's axi4_pins_master_port convention) and drives it cycle-by-cycle from gem5's event queue.

Status

Working end to end: both test programs below pass. CVA6RTLCpu boots CVA6 from boot_addr, executes a real bare-metal RISC-V binary loaded via gem5's RiscvBareMetal workload, and reports the standard riscv-tests tohost pass/fail result back through gem5's exit loop.

Layout

• ext/axiom -- the axiom framework (submodule), including its own vendored ext/gem5 (nested submodule).
• ext/cva6 -- the CVA6 core RTL (submodule, pinned).
• src/cva6/ -- the new SystemVerilog top-level wrapper, the CVA6RTLCpu C++/Python SimObject, and the Verilator build rule.
• scripts/build_gem5.sh -- mirrors src/cva6 into ext/axiom/ext/gem5/src/cva6 (gem5's own SConscript walk needs a real directory, not a symlink -- see axiom's own CLAUDE.md for why).
• configs/cva6/ -- gem5 Python config(s) to run a bare-metal binary on CVA6RTLCpu.
• tests/cva6/ -- two self-checking bare-metal RISC-V test programs (sum, amo_test) using the standard riscv-tests tohost convention, plus two standalone Verilator testbenches that exercise cva6_top directly, independent of gem5: tb_cva6_boot.cc (reset + first fetch only) and tb_cva6_run.cc (runs a full program against an in-process AXI4 memory responder).

Build

make submodules   # git submodule update --init --recursive
make toolchain     # download a portable RISC-V GCC toolchain (no sudo needed)
make verilate       # build src/cva6's RTL via Verilator
make gem5           # mirror sources into gem5 + scons build -> build/RISCV/gem5.opt
make test1           # run tests/cva6/sum.elf, expect "SUCCESS"
make test2           # run tests/cva6/amo_test.elf, expect "SUCCESS"

See axiom's own CLAUDE.md (ext/axiom/CLAUDE.md) for the underlying AXI4 bridge architecture and general gotchas (TARGET_CFG re-verilation, Param-shadowing, etc); src/cva6/'s source comments cover the CVA6-specific details (the SV wrapper's pin convention, the config package's non-idempotent-MMIO override, the boot_addr/hart_id pins).