Xcore ai support

.gitignore

@@ -1,19 +1,51 @@
-**.build*/*
-**/bin/*
-*.o
-*.xe
+# Tmp files & logs
+*.settings
+*.bin
+*.zip
+*.log
 *.vcd
-*.s
+*.swp
+*.*~
+*.xmt
+*.swo
+*.swn
+*~
+*.DS_Store
+
+# Python
+*.pyc
+**/*.egg-info/
+**/.venv*/
+.python-version
+
+# XMOS temp files
+**/*build*/*
+*/bin/*
+**/flash_bin_node*
+**/fw-*
+**/s2l-*
+**/spanning-xn-*
+**/target-xn*
 *.xi
+*.o
 *.i
 *.a
-**/_build/*
-lib_lcd/doc/rst/_build/*
-**/run_*.log
+*.d
+*.decouple
+*.pca.xml
+**/CMakeFiles/*
+
+# XMOS binaries
+*.xe
+
+# Built documentation
+doc/_build/pdf/*.pdf
+**/doc/pdf/*.pdf
 **/pdf/*
 **/html/*
-Installs/*
-.settings*
-examples/lcd_demo/.build*/*
-*.swp
-examples/sdram_demo/.build*
+
+# Testing
+tests/expect
+tests/logs
+tests/result
+tests/test_*/**/*.xn

CMakeLists.txt

@@ -0,0 +1,7 @@
+cmake_minimum_required(VERSION 3.21)
+include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake)
+project(lib_sdram)
+
+add_subdirectory(examples)
+add_subdirectory(tests)
+add_subdirectory(tools)

README.rst

@@ -4,8 +4,8 @@ SDRAM Library
 SDRAM Libary
 ------------
 
-The XMOS SDRAM library is designed for read and write access of arbitrary length 32b long word buffers at up to 62.5MHz clock rates. 
-It uses an optimized pinout with address and data lines overlaid along with other pinout 
+The XMOS SDRAM library is designed for read and write access of arbitrary length 32b long word buffers at up to 62.5MHz clock rates.
+It uses an optimized pinout with address and data lines overlaid along with other pinout
 optimizations to implement 16 bit read/writes to Single Data Rate (SDR) SDRAM devices of size up to 256Mb,
 while consuming a total of just 20 xCORE I/O pins.
 
@@ -46,9 +46,7 @@ Related application notes
 .........................
 
 - I/O Timings for xCORE200 [#]_.
+- I/O Timings for xcore-ai [#]_.
 
 .. [#] https://www.xmos.com/download/private/I-O-timings-for-xCORE200%281.0%29.pdf
-
-
-
-
+.. [#] https://www.xmos.com/download/xcore_ai-I-O-Timings(7).pdf/

examples/CMakeLists.txt

@@ -0,0 +1,5 @@
+cmake_minimum_required(VERSION 3.21)
+include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake)
+project(lib_sdram_examples)
+
+add_subdirectory(sdram_demo)

examples/sdram_demo/CMakeLists.txt

@@ -0,0 +1,16 @@
+cmake_minimum_required(VERSION 3.21)
+include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake)
+project(sdram_demo)
+
+set(APP_HW_TARGET           SLICEKIT-XC200-X1.xn)
+#set(APP_HW_TARGET           xcore_ai_sdram_test_board.xn)
+
+set(APP_DEPENDENT_MODULES   "lib_sdram")
+set(APP_INCLUDES src)
+set(APP_COMPILER_FLAGS      -g -O2)
+
+set(APP_PCA_ENABLE          ON)
+
+set(XMOS_SANDBOX_DIR        ${CMAKE_CURRENT_LIST_DIR}/../../..)
+
+XMOS_REGISTER_APP()

examples/sdram_demo/config.xscope

@@ -1,2 +1,2 @@
-<xSCOPEconfig enabled="true" ioMode="basic">
-</xSCOPEconfig>
+<xSCOPEconfig enabled="true" ioMode="basic"></xSCOPEconfig>
+<!-- xSCOPEconfig enabled="false" ioMode="none"></xSCOPEconfig -->

examples/sdram_demo/src/sdram_demo.xc

@@ -66,9 +66,20 @@ void application(streaming chanend c_server) {
 }
 
 //Use port mapping according to slicekit used
-#ifdef __XS2A__
+#if defined(__XS3A__)
+// SDRAM test board for XU316
+#define CLOCK_DIV   5 // (600/ (5*2)) = 60.0MHz
+#define SERVER_TILE 1
+on tile[SERVER_TILE] : out buffered port:32   sdram_dq_ah                 = XS1_PORT_16A;
+on tile[SERVER_TILE] : out buffered port:32   sdram_cas                   = XS1_PORT_1A;
+on tile[SERVER_TILE] : out buffered port:32   sdram_ras                   = XS1_PORT_1P;
+on tile[SERVER_TILE] : out buffered port:8    sdram_we                    = XS1_PORT_1M;
+on tile[SERVER_TILE] : out port               sdram_clk                   = XS1_PORT_1F;
+on tile[SERVER_TILE] : clock                  sdram_cb                    = XS1_CLKBLK_1;
+#elif defined(__XS2A__)
 //Triangle slot tile 0 for XU216
-#define      SERVER_TILE            0
+#define CLOCK_DIV   4 // (500/ (4*2)) = 62.5MHz
+#define SERVER_TILE 0
 on tile[SERVER_TILE] : out buffered port:32   sdram_dq_ah                 = XS1_PORT_16B;
 on tile[SERVER_TILE] : out buffered port:32   sdram_cas                   = XS1_PORT_1J;
 on tile[SERVER_TILE] : out buffered port:32   sdram_ras                   = XS1_PORT_1I;
@@ -77,7 +88,8 @@ on tile[SERVER_TILE] : out port               sdram_clk                   = XS1_
 on tile[SERVER_TILE] : clock                  sdram_cb                    = XS1_CLKBLK_2;
 #else
 //Square slot on A16 slicekit
-#define      SERVER_TILE            1
+#define CLOCK_DIV   4  // (500/ (4*2)) = 62.5MHz
+#define SERVER_TILE 1
 on tile[SERVER_TILE] : out buffered port:32   sdram_dq_ah                 = XS1_PORT_16A;
 on tile[SERVER_TILE] : out buffered port:32   sdram_cas                   = XS1_PORT_1B;
 on tile[SERVER_TILE] : out buffered port:32   sdram_ras                   = XS1_PORT_1G;
@@ -89,20 +101,23 @@ on tile[SERVER_TILE] : clock                  sdram_cb                    = XS1_
 int main() {
   streaming chan c_sdram[1];
   par {
-      on tile[SERVER_TILE]:sdram_server(c_sdram, 1,
+    on tile[SERVER_TILE]:{
+      set_core_high_priority_on();
+      sdram_server(c_sdram, 1,
               sdram_dq_ah,
               sdram_cas,
               sdram_ras,
               sdram_we,
               sdram_clk,
               sdram_cb,
 #if USE_256Mb
-              2, 256, 16, 9, 13, 2, 64, 8192, 4); //IS45S16160D 256Mb option or similar
+              //IS45S16160D 256Mb option or similar
+              2, 256, 16, 9, 13, 2, 64, 8192, CLOCK_DIV);
 #else
-              2, 128, 16, 8, 12, 2, 64, 4096, 4); //Uses IS42S16400D 64Mb part supplied on SDRAM slice
+              //Uses IS42S16400D 64Mb part supplied on SDRAM slice
+              2, 128, 16, 8, 12, 2, 64, 4096, CLOCK_DIV);
 #endif
-                                                  //Note clock div 4 gives (500/ (4*2)) = 62.5MHz
-
+    }
     on tile[SERVER_TILE]: application(c_sdram[0]);
     on tile[SERVER_TILE]: par(int i=0;i<6;i++) while(1); //Consume the remaining MHz
   }

examples/sdram_demo/xcore_ai_sdram_test_board.xn

@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Network xmlns="http://www.xmos.com"
+         xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+         xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
+  <Type>Board</Type>
+  <Name>xcore-ai SDRAM Test Board</Name>
+
+  <Declarations>
+    <Declaration>tileref tile[2]</Declaration>
+  </Declarations>
+
+  <Packages>
+    <Package id="0" Type="XS3-UnA-1024-FB265">
+      <Nodes>
+        <Node Id="0" InPackageId="0" Type="XS3-L16A-1024" Oscillator="24MHz" SystemFrequency="600MHz" ReferenceFrequency="100MHz">
+          <Boot>
+            <Source Location="SPI:bootFlash" />
+          </Boot>
+          <Tile Number="0" Reference="tile[0]">
+            <!-- XUD Ports -->
+            <Port Location="XS1_PORT_1H"  Name="PORT_USB_TX_READYIN"/>
+            <Port Location="XS1_PORT_1J"  Name="PORT_USB_CLK"/>
+            <Port Location="XS1_PORT_1K"  Name="PORT_USB_TX_READYOUT"/>
+            <Port Location="XS1_PORT_1I"  Name="PORT_USB_RX_READY"/>
+            <Port Location="XS1_PORT_1E"  Name="PORT_USB_FLAG0"/>
+            <Port Location="XS1_PORT_1F"  Name="PORT_USB_FLAG1"/>
+            <Port Location="XS1_PORT_8A"  Name="PORT_USB_TXD"/>
+            <Port Location="XS1_PORT_8B"  Name="PORT_USB_RXD"/>
+            <!-- SPI Ports -->
+            <Port Location="XS1_PORT_1A" Name="PORT_SPI_MISO"/>
+            <Port Location="XS1_PORT_1B" Name="PORT_SPI_SS"/>
+            <Port Location="XS1_PORT_1C" Name="PORT_SPI_CLK"/>
+            <Port Location="XS1_PORT_1D" Name="PORT_SPI_MOSI"/>
+          </Tile>
+          <Tile Number="1" Reference="tile[1]">
+          </Tile>
+        </Node>
+      </Nodes>
+    </Package>
+  </Packages>
+
+  <ExternalDevices>
+    <Device NodeId="0" Tile="0" Name="bootFlash" Class="SPIFlash" Type="AT25SF161">
+      <Attribute Name="PORT_SPI_MISO" Value="PORT_SPI_MISO" />
+      <Attribute Name="PORT_SPI_SS" Value="PORT_SPI_SS" />
+      <Attribute Name="PORT_SPI_CLK" Value="PORT_SPI_CLK" />
+      <Attribute Name="PORT_SPI_MOSI" Value="PORT_SPI_MOSI" />
+    </Device>
+  </ExternalDevices>
+
+  <JTAGChain>
+    <JTAGDevice NodeId="0"/>
+  </JTAGChain>
+
+</Network>

lib_sdram/api/sdram.h

@@ -51,6 +51,56 @@ void sdram_server(streaming chanend c_client[client_count],
         const static unsigned refresh_cycles,
         const static unsigned clock_divider);
 
+/**
+ * Same as ``sdram_server``, but with a non-const-static clock divider
+ * and additional timing parameters adjusting the data input window.
+ * ``sdram_server`` uses defaults for these parameters depending on the clock divider.
+ * Refer to tools/sdram_timing_calculations for more information.
+ *
+ *  \param c_client             This is an ordered array of the streaming channels to the clients. It is in client
+ *                              priority order(element 0 being the highest priority).
+ *  \param client_count         The number of clients.
+ *  \param dq_ah                The data and address bus port.
+ *  \param cas                  The CAS signal port.
+ *  \param ras                  The RAS signal port.
+ *  \param we                   The WE signal port.
+ *  \param clk                  The SDRAM clock.
+ *  \param cb                   Clock block to control the ports.
+ *  \param cas_latency          The CAS latency.
+ *  \param row_words            The number of 32b words in a SDRAM row (half the number of columns).
+ *  \param col_bits             The count of bits for a memory location, normally 16.
+ *  \param col_address_bits     The number of bits in the column address bus.
+ *  \param row_address_bits     The number of bits in the row address bus.
+ *  \param bank_address_bits    The number of bits in the bank address bus.
+ *  \param refresh_ms           The count of milliseconds for a full refresh cycle.
+ *  \param refresh_cycles       The count of refresh instructions per full refresh cycle.
+ *  \param clock_divider        The divider of the system clock to the SDRAM clock.
+ *  \param read_delay_whole_clocks The number of SDRAM clock cycles (Tclk) to defer input reading
+ *  \param sample_delay         1 for an extra 1/2 Tclk input reading delay, 0 for none
+ *  \param pad_delay            The number of core clock cycles (Tcore) to delay the input signal,
+ *                              in range 0..5. This has the effect of reading input earlier.
+ **/
+void sdram_server_with_delays(streaming chanend c_client[client_count],
+        const static unsigned client_count,
+        out buffered port:32 dq_ah,
+        out buffered port:32 cas,
+        out buffered port:32 ras,
+        out buffered port:8 we,
+        out port clk,
+        clock cb,
+        const static unsigned cas_latency,
+        const static unsigned row_words,
+        const static unsigned col_bits,
+        const static unsigned col_address_bits,
+        const static unsigned row_address_bits,
+        const static unsigned bank_address_bits,
+        const static unsigned refresh_ms,
+        const static unsigned refresh_cycles,
+        unsigned clock_divider,
+        unsigned read_delay_whole_clocks,
+        unsigned sample_delay,
+        unsigned pad_delay);
+
 /**
  * This is used to initialise the sdram_state that follows the channel to the SDRAM server. It must only be called
  * once on the s_sdram_state that it is initialising. A client must have only one s_sdram_state that exists for the

lib_sdram/lib_build_info.cmake

@@ -0,0 +1,13 @@
+set(LIB_NAME lib_sdram)
+set(LIB_VERSION 3.3.0)
+set(LIB_INCLUDES api src)
+
+set(LIB_DEPENDENT_MODULES "")
+
+set(LIB_COMPILER_FLAGS -O3
+                       -Wno-unusual-code
+                       -fasm-linenum
+                       -fcomment-asm
+                       -g)
+
+XMOS_REGISTER_MODULE()

lib_sdram/src/io.S

@@ -1,7 +1,8 @@
 // Copyright 2014-2021 XMOS LIMITED.
 // This Software is subject to the terms of the XMOS Public Licence: Version 1.
 .text
-#ifdef __XS2A__
+
+#if defined(__XS2A__) || defined (__XS3A__)
 //xCore 200 optimised version with support for >8bit row addresses
 .cc_top sdram_block_write.function
 .align 4
@@ -185,7 +186,7 @@ sdram_block_write:
 
 //////////////////////////////////////////////////////////////////
 
-#ifdef __XS2A__
+#if defined(__XS2A__) || defined (__XS3A__)
 //xCore 200 optimised version with support for >8bit row addresses
 .cc_top sdram_block_read.function
 .align 4
@@ -202,7 +203,7 @@ sdram_block_read:
 	//r2 t0	- start time
 	//r3 word_count
 	//sp[1] row_words
-	//sp[2] cas_latency
+	//sp[2] read_time_offset
 
 #define ras	 			r0
 #define dq_ah	 		r1
@@ -222,7 +223,7 @@ sdram_block_read:
 	sub new_buf_ptr, r0, 0
 
 	//set the first input time (t+CAS+N)
-	ldw temp, 	sp[READ_STACK_WORDS+2]	//cas_latency
+	ldw temp, 	sp[READ_STACK_WORDS+2]	//read_time_offset
 	add start_time, r2, temp
 
 	//calculate the time to issue the terminate cmd
@@ -306,15 +307,15 @@ sdram_block_read_cleanup:
 sdram_block_read:
 .issue_mode single
 #define READ_STACK_WORDS 6
-    
+
     ENTSP_lu6 READ_STACK_WORDS
 
  	//r0 buffer pointer
 	//r1 sdram_ports struct
 	//r2 t0	- start time
 	//r3 word_count
 	//sp[1] row_words
-	//sp[2] cas_latency
+	//sp[2] read_time_offset
 
 #define ras	 			r0
 #define dq_ah	 		r1
@@ -339,7 +340,7 @@ sdram_block_read:
 	ldaw temp, r0[-temp]
 	set dp, temp
 
-	ldw temp, 	sp[READ_STACK_WORDS+2]	//cas_latency
+	ldw temp, 	sp[READ_STACK_WORDS+2]	//read_time_offset
 	add start_time, r2, temp
 
 	//calculate the time to issue the terminate cmd