feat(pio): implement TX/RX FIFO join (FJOIN_TX / FJOIN_RX)

[begeistert]

Problem

The PIO state machines always expose two fixed 4-deep FIFOs and ignore the FJOIN_TX / FJOIN_RX bits in SHIFTCTRL. Programs that merge the two halves into a single 8-deep FIFO — a common idiom for deeper TX buffering or RX capture — observe the wrong depth, FLEVEL, and FSTAT full/empty flags.

Change

• FIFO gains an adjustable usable depth (setCapacity) on top of its allocated buffer; full / size now honour it.
• StateMachine allocates 8-deep FIFOs and applies the join configuration via updateFifoJoin() on construction and on every SHIFTCTRL write. The joined direction becomes 8 deep, the donated direction is disabled (depth 0, reads back as both empty and full), and reconfiguring the join empties both FIFOs — matching the RP2040 datasheet (§3.5.4).

Tests

Adds tests covering the 8-deep TX and RX joins, overflow / TXOVER behaviour, the disabled opposite direction, and FIFO clearing on reconfiguration.

---

For context: this came out of RP2040Sharp, a C# port of rp2040js, while differential-testing the PIO against real RP2040 silicon — the FIFO-join semantics here were validated against hardware. Contributing it back upstream.