arm64: dts: allwinner: wirenboard85x: park CPU at a boot-safe OPP across suspend#362
Closed
evgeny-boger wants to merge 1 commit into
Closed
arm64: dts: allwinner: wirenboard85x: park CPU at a boot-safe OPP across suspend#362evgeny-boger wants to merge 1 commit into
evgeny-boger wants to merge 1 commit into
Conversation
…oss suspend On suspend-to-off resume, U-Boot SPL's board init runs before the resume branch and programs VDD-CPU to its 0.90 V cold-boot value (CONFIG_AXP_DCDC2_VOLT=900); BL31 then re-locks PLL_CPUX to the frequency the kernel parked at. Under schedutil the suspend-entry work (fs sync, freezing) spikes the load, so the kernel routinely parks at a 1.00-1.10 V OPP (up to 1416 MHz) — leaving the cluster up to 200 mV under-volted until cpufreq's resume rewrites the regulator ~2 s later. The resulting fetch/load transients during secondary bringup were the WB8 post-resume corruption family (fetch faults on valid code words, single-bit pointer flips, bringup lockups — always within ~2 s of resume, with retained-DRAM CRC clean on every failing cycle). Mark the 480 MHz OPP as the suspend OPP: cpufreq_generic_suspend() parks there before the PSCI call. 480 MHz is rated 0.90 V and present on every speed bin (opp-supported-hw 0x1f), so the parked frequency is safe at SPL's boot voltage even if the firmware-side fix is absent or the boot voltage changes. Costs a few hundred ms of resume latency until the governor revives. The primary fix is in BL31 (restores the recorded voltage before the recorded frequency); this is the kernel-side belt so firmware and kernel cannot skew apart. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Member
Author
|
Superseded by #363 — the opp-suspend commit is now the final commit of the single consolidated kernel series (same content, checkpatch-clean, rebased onto the series base). Closing. 🤖 Generated with Claude Code |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Kernel-side belt for the WB8.5 suspend-to-off resume voltage contract: SPL programs VDD-CPU to 0.90 V on the resume path while BL31 restores the kernel-parked PLL frequency (up to 1416 MHz). Parking at the bin-universal 0.90 V-rated 480 MHz OPP across suspend (
opp-suspend) keeps the resume window safe even if firmware and kernel versions skew. The primary fix is firmware-side (wirenboard/arm-trusted-firmware#4, restores the recorded voltage before the recorded frequency) — this PR is standalone and safe with or without it. Verified:sun50i-h616-wirenboard851.dtbbuilds and carries the property (fdtget-checked).Root-cause evidence: 10 corruption samples (fetch faults on valid code, single-bit pointer flips, CPU-bringup lockups, always <2 s post-resume, DRAM CRC clean every time), root-caused and eliminated on the bench 2026-07-10 (210+ clean cycles since).
🤖 Generated with Claude Code