transient_setup_help.html

<!doctype html><html><head><meta charset="utf-8"><meta name="viewport" content="width=device-width,initial-scale=1"><title>Quick PI transient setup</title><style>body{font:16px Arial;max-width:1000px;margin:24px;line-height:1.5}table{border-collapse:collapse}td,th{border:1px solid #bbb;padding:8px;text-align:left}code{overflow-wrap:anywhere}svg{max-width:100%;height:auto}</style></head><body><h1>WayriCAD Quick PI transient load steps</h1>
<p>This is an explicit lumped R/L/C model with prescribed current steps or bank-only linear current ramps. It does not derive inductance, capacitance or switching edges from a DC copper solution.</p>
<h2>Individual shunt capacitors</h2><p>In transient setup, select a load and open <b>Shunt capacitors for selected load…</b>. Enter each effective C, ESR and total part + connection ESL. This bank replaces aggregate C/ESR. Choose the actual return to review saved-board candidates; no part is included automatically. Unit-bearing values can prefill, while ESR, ESL and derating remain explicit.</p><p>Use a finite prescribed load-current rise for all-inductive feed/shunt paths; an ideal step needing an impulse is rejected. Quick/advanced mode and JSON retain the bank. <b>Capacitor response</b> and HTML tables select per-part internal C voltage, branch current and ESR heat; half-step differences remain evidence, not convergence proof.</p><p>Values describe a lumped ideal-return model, not extracted capacitor placement or cross-rail dynamics. Standalone prescribed-current transients only; coupled electrothermal bank stepping and converter control are unsupported.</p><img src="help-shunt-capacitors.png" width="850" alt="Native individual C ESR ESL editor with finite current rise"><img src="help-shunt-response.png" width="1000" alt="Solved selected capacitor internal voltage and branch current"><p><a href="studies/transient-shunt-bank.json">Explicit JSON example</a> · <a href="README.md#individual-shunt-capacitors-in-transient-studies">Inputs, CLI and capture provenance</a></p><h2>Quick setup</h2><ol><li>Choose source and load units in Quick PI, then open the transient study.</li><li>Use mΩ, nH, µF and µs in the quick editor. Enter the actual effective capacitance and ESR for each load node. Zero L deliberately disables that inductance term.</li><li>A matching feasible single-load DC result can seed one total-path resistor. It is not regulator output resistance: keep the same path out of the branch-R entry to avoid double counting. Multi-load paths and nonlinear drops are not collapsed to an invented resistor.</li><li>Set before/after current and the ideal step time, simulation duration and integration step. The initial 100 µs window and 0.1 µs step are editable starting values.</li><li>Choose Recommend time step, then Run transient. If the suggested step exceeds the interval budget, shorten the window or revise the model; the tool does not silently coarsen it.</li><li>Review voltage/current plots, source/voltage limits, energy/charge balance and the half-step refinement check before export.</li></ol>
<p>The Advanced SI editor retains the full Ω/H/F/s grid. You can switch modes even while required values are missing. Explicit JSON input/output makes the same reviewed model reusable through the CLI.</p>
<h2>Aggregate capacitor circuit and equations</h2><svg viewBox="0 0 850 200" width="850" height="200"><g stroke="#315b7d" fill="none" stroke-width="3"><path d="M20 50h90m150 0h70m150 0h120m0 0h150M600 50v45m0 60v30M20 185h750M740 50v135"/><rect x="110" y="28" width="150" height="44"/><rect x="330" y="28" width="150" height="44"/><rect x="560" y="95" width="80" height="60"/></g><g font-family="Arial" font-size="16" fill="#17202a"><text x="20" y="25">Vs</text><text x="126" y="56">Rsource, Lsource</text><text x="350" y="56">Rpath, Lpath</text><text x="573" y="119">ESR</text><text x="586" y="141">C</text><text x="650" y="28">Load node</text><text x="755" y="125">Iload(t)</text><text x="20" y="168">Ideal return</text></g></svg>
<p>For branch supply currents i, capacitor voltages v and prescribed load currents d:</p><p><code>L di/dt + R i + v = Vs·1 + ESR·d</code><br><code>C dv/dt = i − d</code></p><p><code>L = diag(Lpath) + Lsource·11ᵀ</code><br><code>R = diag(Rpath + ESR) + Rsource·11ᵀ</code></p><p>Kirchhoff current balance gives capacitor current i−d; capacitor voltage integrates that current divided by C. Inductor voltage is L di/dt. Shared source R/L couples the branches. Load-node voltage includes the capacitor ESR jump, so it need not equal the capacitor's stored voltage.</p>
<p>For individual banks, each branch has its own capacitor voltage and charging current, with series ESR/ESL. The aggregate capacitor trace is only a capacitance-weighted mean. The generalized network below retains each branch and finite-ramp forcing.</p><h2>Individual-bank equations</h2><p>Let q be charging-positive capacitor currents, v individual internal capacitor voltages, d prescribed load demands and A map capacitor branches to load nodes. Feed currents are i = A q + d. P and Q contain shared/path inductance and resistance.</p><pre>M = diag(ESL) + Aᵀ P A
R = diag(ESR) + Aᵀ Q A
M q′ + R q + v = Vs·1 − Aᵀ Q d − Aᵀ P d′
diag(C) v′ = q
Vload = Vs·1 − Q i − P i′</pre><p>Finite linear ramps have explicit slopes d′. Each branch stores its own electric and magnetic energy. Exact algebraic constraints handle ideal branches, and incompatible instantaneous steps are rejected. Shared-source R/L couples load nodes; unknown return or connection paths are not inferred.</p><h2>Time integration</h2><p>Initialization is the pre-step DC equilibrium at the Before currents; this is not an arbitrary capacitor-startup or discharge model. The existing solver uses backward Euler, retains ideal step-event samples and compares a half-step run. The setup helper computes finite eigenvalues of the passive descriptor system and suggests twenty samples per fastest e-fold/radian plus at least 1,000 intervals per window. This is a starting heuristic, not proof of convergence. Numerical backward-Euler damping is accounted separately from physical resistor heating.</p>
<h2>What is excluded</h2><p>The bank model supports explicit capacitor ESL and prescribed linear current ramps. Switching converter dynamics, arbitrary current waveforms, constant-power control, source CV/CC transition, 3D time-domain fields and inferred PCB L/C remain unsupported. Supply current budgets are diagnostics, not a simulated current-limit controller. Use reviewed parasitic values and independently check the assumptions.</p><h2>Recall this study</h2><p><b>Save setup…</b> and <b>Load setup…</b> retain this dialog’s editable inputs separately from computed results. The chooser starts in the PCB project folder and proposes a filename specific to this study mode. Loading clears prior results; run a fresh analysis after reviewing inputs. Use <b>Load simulation…</b> to inspect a completed result without solving. Raw model JSON actions remain separate CLI exchanges. <a href="STUDY_SETUP_FILES.md">Setup file guide</a>.</p></body></html>