WayriCAD

PCB design, analysis and project review in KiCad. Choose from 24 independently installable plugins in the source catalogue. Processing runs locally after setup. KiCad 10 is the validated target.

The download counter updates automatically across all releases. It includes direct GitHub downloads and KiCad PCM downloads, since PCM fetches the same GitHub release assets. It counts downloaded files, including repeat downloads and release metadata, not unique users or installations. GitHub does not separate PCM from direct downloads; automatic source ZIP/tar downloads and repository clones are excluded.

New in 3.6.42: connector mating reviews, matching schematic labels, CSV-to-label conversion and physical pinout grids in Pin Extractor. Release notes.

New in 3.6.42

Pin Extractor addition	Where to start
Mating connector pairs	Top/bottom views, poses and contact mapping
Matching labels	Editable modifiers, bulk assignment and individual rows
CSV / TSV to schematic labels	Numbering and global/local/hierarchical labels
Physical pinout tables	Actual connector rows and columns

Recent Quick-tool improvements and measured speeds · 3.6.41

Improvement	Where to start
Faster analysis	PI measurements · SI measurements · Thermal measurements
Guided Joule feedback	Materials, cooling and model limits
Complete analysis workflows	Marble and White Rabbit tutorials · Detailed guides
Blender visualization	Export supported board geometry, fields and thermal frames

Study	Before	3.6.41
Fresh Quick SI analysis — Marble	7.09 s	3.77 s
Fresh Quick SI analysis — White Rabbit	1.52 s	0.52 s
Marble multilayer thermal solve	93.07 s	65.02 s
PI 3D field preparation benchmark	80.9 ms	18.2 ms

These local measurements cover the stated operations, not total startup for every board. SI serialized results and the compared thermal values matched. See the measurement links above for inputs, methods and numerical tolerances.

Download 3.6.42 · Connector validation and known limits

Start here

What you need	Where to go
Install the tools	Quick steps · Installation guide
Run your first analysis	Getting started
Download or update	Release 3.6.42 · Release notes
Place silkscreen labels	Silkscreen Label Placer · Quick start
Choose a tool	All 24 plugins
See the interfaces	Showcase · Screenshots by plugin
Find detailed instructions	Full user guide
Review algorithms and research	Methods, sources and verification by tool
Resolve a problem	Help and upgrades
Automate or contribute	Development

Detailed analysis guides

Tool	Step-by-step user guide	Offline version
Quick PI	DC paths, returns, AC losses, PDN, transients and probes	HTML guide
Quick SI	Signal paths, returns, coupling, pair timing and IBIS export	HTML guide
QuickTherm	Power inputs, cooling, steady state, transients and temperature inspection	HTML guide

Each guide covers setup, result interpretation, examples, command-line use, report export and troubleshooting, including the limits of each solver.

Follow the Marble and White Rabbit example-board preparation for pinned sources, native-import limits and links to the worked tutorials and control references.

Blender visualization — included in 3.6.41: completed Quick PI, Quick SI and QuickTherm results can be exported as Blender scenes, with supported fields and stored-frame thermal animation. See the Blender walkthrough for the plugin actions, CLI, animation controls and model limits.

Showcase

Click a screenshot for its full resolution. More screenshots, grouped by plugin.

Quick PI — Marble board preview	QuickTherm — 3D temperature view
Geometry preview; no PI field solved.	Assumed-load demonstration; STEP models disabled.
Quick PI — AC setup · 3.6.40	Quick PI — AC heating · 3.6.40
Live explicit-geometry preview before solving.	Computed illustrative loop; 128.1 mW total copper heat.
Trace Refiner — old/new comparison	Fanout — connector escape preview
Synthetic fixture; native validation reported no new DRC findings.	Six-pin synthetic fixture; dense Marble trial results.

Released workflow highlights

Refresh the WayriCAD repository in Plugin and Content Manager, install updates, then restart PCB Editor.

Improvement	Workflow
Computed thermal playback	Default 0.1 s frames, separate solver/output intervals, Previous/Next and playback speed controls. QuickTherm guide.
Reviewed IBIS circuits	Load exact source/receiver models, export selected complete routes and copy a native KiCad circuit. SI workflow and limits.
PI melting and bottlenecks	Trace-cell and via-barrel adiabatic melting estimates, limiting-region selection and heat maps. Melting does not establish fuse opening. PI guide.
SI neighbour map	Search nearby traces, inspect gap/parallel overlap and review supported local coupling separately from geometric exposure. SI guide.
Live Quick PI current	Ctrl+scroll over a sink pad changes that load; other solved copper adjusts total demand. Scroll zooms. A cursor readout compares before/after values. Controls and model limits.
Dense-board Fanout	Native padstack/track/arc checks, real keepout polygons, faster connector exits and retained short-stub continuation. Marble results.
Simpler Constraint Studio	Ordinary rules and netclasses stay in KiCad; Studio retains a read-only overview, protocol presets, matrices, reusable sets and reviewed export. Guide.
Fanout corrections	Accept nullable saved netclass assignments and reject duplicate Fixed-mode launches on connected pads. Real-board trial results and remaining limits.
Updated guides and showcase	Refreshed navigation for all 24 plugins, retained earlier previews and added current native screenshots.
Guard via stitching	Fence selected signal nets/traces on a distinct guard net; review pitch, offset, clearances and rejections. Guide.
Guided, cancellable Fanout	Actual component thumbnails, Before/After and small-window actions. Guide.
Shared responsiveness	Faster dropdowns and exact picking; Quick PI geometry-ready time 33.09 s to 20.26 s. Measurements and limits.
Assistant — testing	Local fuzzy command planning, clarification and reports across registered CLI actions. Guide.
Faster fresh PI solves	Reuse one native PCB across a multi-net batch and reduce geometry/matrix overhead. Marble cold median 43.24 s to 31.71 s. Measurements.
Responsive native board view	Saved silkscreen retains its physical size and placement. Marble full viewport redraw 763 ms to 58 ms; cached drag and indexed probes reduce interaction work. Measurements.
Live, faster fanout preview	Selection and style changes update the main canvas and a component thumbnail. Fixed Marble U35 planning 21.94 s to 0.29 s with identical plans. Fanout guide.
Faster Quick PI interaction	Reuse unchanged results, load selected-net display geometry in the worker, and retain plot artists during navigation. Measurements.
Better net selection and views	Search with wildcards or fuzzy suggestions without losing the selected net. Focus maps and PCB selection on the simulated nets; choose a combined-layer projection.
Clear trace comparisons	Trace Refiner 0.3.1 fixes missing UUID-setter compatibility and provides amber/teal Overlay, Before, After and Side-by-side views.
Pad/via endpoint centering	Run the separate Trace Refiner action for pad/via endpoint centering. Trace Refiner guide.
Readable local silkscreen	Preserve acceptable references; try footprint-axis placement, bounded sizing and local repacking near the owning courtyard. Every eligible reference receives an outcome. Silkscreen guide.
Managed silkscreen guides	Leaders default off. Optional short straight guides have persistent ownership, detached-guide auditing and reversible cleanup. CLI HTML reports show both board faces. Silkscreen guide.
Shared-return PI and multi-pad units	Solve common return copper across rails; choose multiple physical source/load pads per unit. Shared return losses count once. PI guide.
Automatic mesh sizing	PI and thermal models recommend sizes and refine supported regions locally, with manual overrides and explicit budget warnings.
Power and thermal Sankeys	Follow source-to-load power or individual-part dissipation in native actions and offline HTML reports.
PI Joule heating checkbox	Enable temperature feedback, then supply reviewed material and cooling inputs. Plain DC already reports copper losses.
Quick SI local crosstalk	Configure directed aggressor/victim pairs and review supported straight-section coupling, modeled coverage and omitted geometry. SI guide.
PI / SI / Therm reports	Read status, coverage and provenance; search/sort tables, navigate sections and print. Interactive plots and probes remain available.
CLI access across all 24 tools	wayricad tools list, doctor and run TOOL -- --help; includes reviewed analysis jobsets. Command catalogue.
Mechanical Check review	Hideable findings panel, clearer details, direct focus/isolation and separate measurement tools. Mechanical guide.

PI shared returns are fixed-current, fixed-temperature DC models. SI coupling remains a local supported-section screen; it is not a whole-board channel prediction. Automatic geometry sizing is not convergence proof, and 3D sizing stays manual. Release notes.

See screenshots grouped by plugin, offline help for all tools, and panel/table controls.

Analysis evidence

Released tools include jointly solved shared-return copper for multi-net PI, multiple source/load pads per PI unit, and local coupled-line crosstalk analysis for SI. Read the Marble validation results and model limits, PI guide and SI guide before interpreting them as whole-board predictions.

Install and open

1. Open Plugin and Content Manager in KiCad Manager. Add this repository:

   https://raw.githubusercontent.com/wayri/WayriCAD/develop/pcm/repo.json
   

2. Select WayriCAD Plugin Repository and install the tools you want. You can also download a PCM ZIP from Releases and use Install from File, without unpacking it.

3. For IPC tools, enable the API and configure Python in Preferences → Plugins. Allow the first dependency setup to finish, then restart PCB Editor.

4. Open and save your project. Launch a tool from Tools → External Plugins or the toolbar. WayriCAD — All tools… searches the installed tools if the menu is crowded.

Fusion, Variant Manager, Silkscreen Label Placer, Trace Refiner, Component Arranger and Layer Counter use the native plugin loader and do not need the IPC API enabled. First-time setup may need internet access. For setup problems or offline use, use the help table below.

Getting started

Your first task	Quick start	Detailed guide
Check voltage drop and copper losses	Quick PI	PI guide
Check board and component temperatures	QuickTherm	Thermal guide
Screen signal delay and reflections	Quick SI	SI guide
Measure route R, L, C and impedance	Trace RLC	RLC guide
Edit and export a BOM	BOM workflow	BOM guide
Inspect copper and component analytics	Analytics workflow	Analytics guide
Arrange silkscreen labels	Label placement	Silkscreen guide

Save the PCB, refill its zones, and save Board Setup before analysis. Start with one net or a small component group, then expand the study. Unknown results mean an input or model is missing; they are not a pass.

Silkscreen Label Placer — arrange readable labels

1. Install Silkscreen Label Placer from the WayriCAD package feed, or download its 0.3.3 PCM ZIP and use Install from File. Restart PCB Editor.
2. Open WayriCAD Silkscreen Label Placer and choose all eligible labels, problem-only correction or selected parts. Leave References only (R1, C1…) selected to preserve values and manual text. Acceptable labels are preserved and leaders are off by default.
3. Under Options, enable automatic sizing and set a minimum height if needed. Choose allowed orientations and reading directions. Add editable bold, italic or knockout rules for test points and connectors.
4. Click Preview, inspect both board sides and unresolved labels, then Apply labels. Run KiCad DRC before saving. Labels that cannot fit safely stay unchanged.

User guide and formatting examples · Release

Quick PI — check a power path

1. Open WayriCAD Quick PI. In Setup, choose the power net, source pad and sink pad.
2. Enter Source · V and Load · A. Add sink voltage limits or Additional sinks if needed.
3. Leave Automatic mesh enabled for geometry-based sizing, or turn it off to enter a manual mesh edge. Click Preview to inspect the copper, then Run.
4. Inspect Results for voltage drop, current density and losses. Choose a layer, hover for values, and click to pin probes. Use Export for HTML and JSON.

For your first run, use the default layered DC model. Review copper thickness, via plating and mesh refinement before relying on local peaks.

For AC / SMPS copper losses: open More → AC / SMPS copper study, choose a quick loop, enter dimensions and RMS ripple, then click Run. Results open on heating; use Inspect to switch to impedance or the copper/return field. Choose Custom loop for conductor tables or an SMPS harmonic spectrum. AC walkthrough.

QuickTherm — check board and part temperatures

1. Open WayriCAD QuickTherm. In Component inputs, select the parts to include and enter their actual operating power, not their maximum power rating.
2. Use Field mapping… for your property names. Add the thermal resistances and temperature limits needed by the selected model; missing junction paths stay unknown.
3. In Board + results, review the board heat model, materials, ambient temperature and environment. Use Automatic mesh for supported board models, then start with a steady-state study and click Run thermal.
4. Use Top, Bottom or 3D, probe the board and select parts in the temperature table. Export the report. For time-varying heating, open Heating study… to review duration, solver/frame intervals and storage advice, then edit power steps directly in watts.

QuickTherm installs separately from Quick PI. Air, vacuum and other environments need explicit heat-rejection paths; airflow fields are not solved.

Automatic sizing refines supported regions near sources and contacts within the mesh budget. It is a starting recommendation, not proof of convergence. Review the selected sizes and unresolved-feature warnings in the report; compare finer meshes before trusting a local peak. Manual sizing remains available, including for backends without automatic sizing.

Quick SI — screen a routed signal

1. Open WayriCAD Quick SI. Search for a net or use Select net on board.
2. Open Set up path and response… to choose source and receiver pads and review rise time, impedance, dielectric and driver/load assumptions together. Confirm the actual return in the main workspace; other same-part pads are shown for review and are not shorted into an SI endpoint.
3. Click Screen selected path. Inspect delay, routed sections, impedance coverage and reflection estimates; unresolved sections remain visible.
4. Inspect the route and waveform plots, then export HTML/JSON for review.

Automatic timing assumes ideal continuous references where indicated. A mixed route may have usable section results without a single overall impedance.

Trace RLC — measure a routed connection

1. Open Trace RLC / Impedance, choose the net and two different pads.
2. Select Path for connected traces/vias/zones, or Zone/plane for a filled island with a declared current-corridor width. Use Auto reference or select a layer.
3. Run Analyze, then inspect the copper preview and per-section R, L, C and impedance.
4. Export the results. Use Line cross section for manually entered supported CPW, grounded CPW or coupled-stripline geometries.

Automatic board impedance covers supported single-ended microstrip/stripline sections. Differential-pair mode measures paths/skew; it does not automatically extract coupled differential impedance.

BOM Studio workflow — now in Analytics Studio

1. Open WayriCAD Analytics Studio from your saved project.
2. In BOM settings, choose fields, grouping, sorting and DNP filters.
3. Edit fields in BOM workspace, then save the workspace sidecar.
4. Use Exports & templates to preview and export a BOM. Use Review & native sync only when you want reviewed edits written back to the saved KiCad project.

BOM Studio was renamed Analytics Studio; they are one plugin. Existing package IDs and workspace files are retained. Native KiCad exports read saved source; workspace exports can include staged edits.

Analytics Studio — inspect components and copper

1. Open Board, copper & components in Analytics Studio.
2. Review mapped cost, mass and power fields for component analytics.
3. Open Board & copper for board area, layer coverage, net/zone copper areas, track lengths, via counts and per-component pad-contact areas.
4. Search by net or part, inspect unknowns, and export the tables as CSV, XLSX, JSON or HTML.

Board analytics uses saved geometry and saved zone fills. Pad-contact area means nominal copper land area, not thermal conductance. Missing values and mixed currencies stay explicit.

All 24 plugins

All 24 plugins are available in release 3.6.42. Assistant is marked testing; individual package versions and runtime requirements are in their guides. Select a plugin for its full guide and supported models.

Plugin	Use it for
WayriCAD Assistant	Plain-English tool selection, visual context and reviewed command execution (testing).
Quick PI	Voltage drop, current flow and copper losses.
QuickTherm	Board and component temperatures, heating playback and thermal reports.
Quick SI	Signal delay, reflections, termination and return-path screening.
Trace RLC / Impedance	Route resistance, inductance, capacitance and supported impedance estimates.
Analytics Studio	BOM editing, purchasing tables and board/copper analytics.
Constraint Studio	Protocol presets, clearance matrices, scoped layer profiles and reviewed export.
Project Fusion	Combine projects or circuit blocks and review linked updates.
Variant Manager	Compare, edit, merge and recover assembly variants.
Embed3D	Collect libraries and 3D models for portable projects.
Fanout Generator	Preview and place escape tracks and vias.
Via Stitching	Add reviewed, net-connected stitching vias.
Trace Refiner	Review routing jog cleanup with metrics, focused proposals and exclusions; native connectivity and DRC gate Apply.
Silkscreen Label Placer	Arrange labels with bounded sizing, footprint-axis placement, formatting rules and exceptional short guides.
Component Arranger	Preview compact anchored group placement, side/rotation/density choices and capacitor order; native validation gates Apply.
Layer Counter	Movable copper L1/L2 markers with zone keepouts, 24 styles and explicit mirrored/overlapping core pairs.
Bulk Label Editor	Browse/search PCB nets and connections; review bulk reference, field and PCB-text edits.
Pin Extractor	Export pin tables, connector diagrams and signal maps. Connector mating, physical pin grids and CSV-to-label tools are included in 3.6.42.
Harness Workbench	Map connectors, cables, bundles and wire requirements.
Copper Balancer	Add isolated copper patterns for more even copper density.
Mechanical Check	Inspect 3D collisions, clearances and board assemblies.
Heater Designer	Design and preview PCB or foil heating patterns.
Planar Magnetics	Design PCB coils and screen magnetic/actuator behavior.
Manufacturing Readiness	Check fabrication constraints and prepare manufacturing outputs.

Silkscreen Label Placer is available as an independent native KiCad 10 plugin in the WayriCAD package feed, with its own icon, automatic sizing and formatting rules. See its installation guide.

Plugin previews

Current and earlier screenshots are grouped by tool. Click an image for its original resolution. Demonstration inputs are not predictions for your board; older captures retain generic-path redactions. Current captures and inputs · Earlier capture provenance.

Explore	Previews
Run analyses	Quick PI · QuickTherm · Quick SI · Trace RLC
Improve layout	Fanout · Guard vias · Trace Refiner · Silkscreen
Coordinate tools	Assistant · All plugin guides

WayriCAD Assistant

Interpret a request and review its inputs

The testing package uses local fuzzy matching and registered CLI actions. This plan view is shown before execution; it does not claim a simulation result.

Select exact nets on the saved board

Public Marble, read-only. Exact selected copper is highlighted; zone borders remain outlines. Workflow and native-capture scope.

Quick PI

Marble 3D copper and guided Joule setup · 3.6.41

Native Marble conductivity example: 33,238 tetrahedra, 5,000 displayed samples and an imposed 0.2 A load. Reproduce the study.

Materials and cooling for Joule feedback

Setup preview with illustrative physical inputs. PI's coupled thermal backend still rejects Marble's slots and nonplated holes; this image is not a solved coupled temperature result. The guide includes a runnable explicit steady Joule example and a separate control reference.

Simpler AC setup and results · 3.6.40

Choose a loop and enter its dimensions, DC current and RMS ripple. The main Run button uses the visible recipe. Custom conductor, waveform and mesh controls stay in an expandable section.

Four summary cards distinguish total heat, ripple heat, AC voltage drop and RMS current. Select one large chart and drag the divider to resize the plot or table.

Actual explicit 20 mm copper-loop solve at 20 °C: 5 A DC plus 1 A RMS at 100 kHz, 128.1 mW total copper heating and 4.976 mW ripple heating. A single supplied frequency is a discrete result. Workflow · Capture inputs and checks.

Individual shunt capacitor response · 3.6.40

Explicit C/ESR/ESL branches with a finite prescribed load rise; this is a lumped model, not extracted board parasitics. Inputs and numerical checks.

Current mixed loads and grouped pins · 3.6.38

Disposable strip, 3.3 V source, 1.65 W grouped IC load and a separate 0.25 A sink. Actual extracted-copper solve: 0.750252 A total and 1.3862 mW loss. No mesh-convergence claim. Inputs and limitations.

PDN and transient setup · 3.6.38

Explicit lumped source/path R/L and local C/ESR; 0.1→1 A current step. This is a network demonstration, with declared inductance and capacitance. Setup window · PDN capacitor-bank setup · Impedance results.

Earlier AC copper and return losses · 3.6.38

Balanced two-strip cross-section, 5 A DC plus 1 A RMS at 100 kHz; fixed 20 °C copper. The explicit field solve gives 0.128126 W copper loss. Saved-board return geometry is not extracted automatically. Setup.

Ground and return setup: choose Rails / ground returns… for DC ground drop, or Return path for a geometric plane/stitching review. The common controls stay visible and optional settings stay collapsed.

Native synthetic staged inputs; this setup image is not a solved power result.

Earlier Marble geometry preview · 3.6.28

Read-only extracted copper and board context. The editable terminal/operating defaults are not a reviewed power-path study, and no voltage field has been solved.

Board and results workspace

The displayed field solves a uniform copper plate; the routed PCB provides visual context. Capture and reference.

Package contacts and copper losses · 3.6.14

Generated demonstration board with illustrative lead/solder properties. Capture inputs · Contact model.

Research and model references

Reference	Role
MIT conduction chapter	Analytical resistance checks.
Elmer beam fixture	Published numerical benchmark inputs.
Full references	Meshing paper, verification guidance and model limits.
AC / SMPS copper methods	Harmonic skin/proximity and Joule-loss model, explicit returns and HV/LV applicability. Included in 3.6.34.

Report preview

Rendered synthetic example with explicit model/coverage status; not a passed board qualification.

QuickTherm

Marble transient walkthrough · 3.6.41

Real board geometry with illustrative loads, capacities and cooling. The frames show stored solver states at 0, 0.5 and 1 s; U1 switches off at 0.5 s. Setup, timestep selection and playback · Blender animation export.

Guided heating study · 3.6.39

Review power, boundary assumptions and frame costs before applying or running. Inputs and capture scope.

Current component inputs · 3.6.38

Review the included parts, declared loads and limits before running the model. Inputs and capture scope.

Current paired top/bottom inspection · 3.6.38

Generated saved-board example, 1.05 W total and explicit forced-air assumptions. Both faces display one approximate midplane field; the back is mirrored. No bottom-side footprints are present in this example.

Current 3D inspection

STEP loading is off; component markers are illustrative. Inputs and capture scope.

Earlier large QuickTherm captures · 3.6.28

STEP models and transient heating

Calculated board and declared component RC temperatures; each modeled part has one temperature, and grey parts remain unknown. Inputs and validation.

Component inputs

Review power, thermal resistances, limits and analysis scope. Capture notes.

Imported copper/contact heat and fitted controls · 3.6.14

The illustrative 1 s frame includes imported copper and contact losses. Capture inputs · Validation.

Research and model references

Reference	Role
Gmsh research paper (2009)	Optional 3D mesher provenance.
CalculiX manual	Thermal backend input format.
Full references	Package-model context, bridge and limitations.

Report preview

Rendered synthetic example with explicit model/coverage status; not a passed board qualification.

Quick SI

White Rabbit route walkthrough · 3.6.41

Native White Rabbit import: EBI1_NBS3, IC33.J34 to IC6.A9, 62.555 mm. The tutorial declares its uniform-line and driver/receiver assumptions. Worked example and input limits.

Shunt capacitors in native transient circuits · 3.6.40

Manual source/receiver additions to the exported KiCad/ngspice circuit. The built-in illustrative eye does not use these parts. Workflow and limits.

Guided path and response · 3.6.39

Choose the physical path and review explicit assumptions in one form. This is setup on the public Marble board, not a new solved or measured channel. Inputs and capture scope.

Current Marble route and return selection · 3.6.38

U6.8→U54.16, 253.670 mm and three vias. The 1.513645 ns delay uses declared 50 Ω/effective permittivity 3.2, not extracted channel impedance. Native neighbour inspection also shows local geometry and unknown coupling explicitly. Neighbour view · Inputs and capture scope.

Earlier route and protocol captures follow.

Return path: select the actual return below Source/Receiver, or explicitly confirm the suggested domain. Extra nets, pins and reference overrides are in More return options.

Native synthetic route with explicit line assumptions; missing filled return coverage remains unknown.

Routed signal analysis

Inspect the selected signal path and its available results.

Protocol screening

Missing models and reference coverage remain visible.

Research and model references

Reference	Role
TI high-speed layout guidance	Protocol/routing context.
Nubis SignalIntegrity	Optional network interoperability.
Full references	I2C/CAN/DDR sources and shared impedance model.

Report preview

Rendered synthetic example with explicit model/coverage status; not a passed board qualification.

Trace RLC / Impedance

Current Marble electrical coverage · 3.6.38

253.670 mm route, three vias, DC resistance 0.978676 Ω. Partial reference coverage and unknown antipad capacitance remain visible; these are modelled section totals. Route window · Capture scope.

Earlier route and AC examples follow.

Saved-board route analysis

Inspect connected copper and per-section electrical coverage.

AC and geometry analysis

Review the route geometry and conductor-loss estimates.

Research and model references

Reference	Role
Pinned EMerge equations	Scalar cross-section source.
Qucs CPW theory	Conformal-mapping equation reference.
Full references	Microstrip paper, via/plane sources and validation fixtures.

Analytics Studio

Board and copper analytics

Inspect layer/net areas, zones, vias and component pad-contact tables.

Component cost, mass and power · earlier BOM Studio interface

The earlier BOM Studio view is retained here under its current name, Analytics Studio. Missing component data stays explicit.

Constraint Studio

Read-only rule overview

Current source leaves individual rule editing to KiCad's Design Rule Editor and netclass editing to Board Setup. Studio keeps protocol presets, matrices, reusable sets and reviewed project export. This native fallback capture uses the public demonstration fixture. Changes and validation.

Earlier worksheet preview

Historical editable UI rendered from a demonstration snapshot. Scope colours are condition matches, not native DRC results.

Mechanical Check

3D measurements and height checks

The fixture deliberately includes height violations and incomplete coverage. Capture and validation.

Mechanical Check has a hideable findings sidebar, clearer filters and detail cards, direct focus/isolation controls, and separate Measure/Display tabs. See the review workflow.

Trace Refiner

Validated original/proposed comparison · 3.6.28

Disposable five-segment fixture: one proposed replacement, zero new native DRC findings. Existing baseline findings remain visible; validation is not a blanket DRC pass.

After explicit Apply

The first source UUID was retained; Undo restored the original track snapshot. Fixture, validation and capture details.

Clean small routing jogs or center existing pad/via track contacts with selected-track, selected-net, net-filter, net-class and layer scopes. Centering only adjusts an endpoint already touching one unambiguous same-net terminal; actual gaps remain unchanged. Preview keeps routing untouched; native connectivity and before/after DRC must pass before Apply. Differential pairs and protected routing remain unchanged. Available as its own PCM package, with offline Help and a CLI for preview, validation and export to a new project.

Version 0.3.1 includes separate pad/via endpoint centering, metrics, focused review, proposal exclusion and resizable settings and review panels.

Component Arranger

Choose selected parts, PCB groups, schematic sheets or wire clusters; confirm the anchor and highlighted area. Review courtyard-aware placement, capacitor ordering, crossings and length before native validation. Independent package with icon, offline help, adjustable panels and CLI.

Layer Counter

Create physical copper-layer labels as a native movable group with a zone-only keepout. Choose from 24 styles, including mirrored and overlapping core pairs, then Preview and Add. Available in release 3.6.20 as an independently installable package. Setup and CLI.

The shared native preview renderer shows L3/L4 mirrored. These are off-screen preview renders, not window screenshots.

Silkscreen Label Placer

Arrange visible reference labels with a simple Preview → Apply flow. Preserve acceptable labels, then try footprint-axis placement, bounded sizes and staggered edge slots. Leaders are off by default; optional short straight guides are audited and removable. Hidden/locked text stays untouched and unresolved placements remain listed.

Current native canvas render on a public synthetic 100-part fixture; no unresolved labels or guides. The retained window and dense-board captures below show earlier controls.

Sizing, reading direction and formatting

These options stay separate from the simple main workflow. Native fabrication minimums always apply; formatting patterns are editable to match your board.

Fanout Generator

Marble BGA, connector and partial-routing trials record current failures as well as the two reproduced bugs fixed in source. Complete dense-board fanout remains unvalidated; the fixture previews below show narrower workflows.

Connector before and proposed after · 3.6.28

Actual native window on a six-pin generated connector. All six proposals were accepted; Apply created 12 tracks and Undo removed them. This fixture is separate from the full-board Marble trials and does not establish dense-BGA completion.

Guided review on Marble · 3.6.28

Actual accepted candidates appear in teal; existing geometry provides context. This read-only preview is not a completed or DRC-qualified route.

Live style preview

Select components or pins, choose a style and inspect its actual fanouts in the small component preview and main canvas. Apply remains separate.

Adaptive fanout

Review pads, existing copper and proposed tracks/vias before applying.

Planar Magnetics

Motor EMF and winding analysis

Review winding layouts, motor EMF/force and supported simulation models in the guide.

Research and model references

Reference	Role
Reviewed motor research	Published work and implemented/future model distinctions.
Magnetics equation references	Filament and capacitance-matrix checks.

Project Fusion

Guided import

Inspect the detected source scope and proposed changes before applying an import or linked update. Existing layout and schematic update policies remain explicit.

Variant destination choices

Review whether the source variant is merged into a working variant or retained separately.

Variant Manager

Assembly comparison

Compare saved and staged assembly states, with bulk operations and reviewed recovery.

Via Stitching

Guard a selected signal · 3.6.28

Generated two-plane fixture with 22 proposed GND through-vias. Native DRC after refill added no findings. A one-plane negative fixture produced dangling-via warnings; geometric clearance alone does not establish a useful return path. Workflow and limitations.

Embed3D

Review the proposed local libraries and models before exporting a portable project.

Pin Extractor

Choose exact scope and fields, inspect the pin map, then export tables or diagrams.

Harness and Cable Workbench

Review explicit connector and wire mappings; a PCB net alone cannot infer an external cable.

Bulk Label Editor

Current net inventory and text preview · 3.6.38

Marble: 1,374 named nets and 35,765 text fields. The MDC net has two pads, 31 tracks and three vias. Electrical net names are read-only. Reference replacement preview.

Earlier text-review window

Select the text/field scope, review proposed changes and apply them explicitly.

Copper Balancer

Synthetic density example. Inspect exclusions and generated copper before export and native DRC.

PCB / Foil Heater Designer

Current 3.6.38 native preview: 80 × 50 mm serpentine, 35 µm copper, 12 V; 3.940 Ω and 36.55 W illustrative electrical loading. No thermal solve or apply.

Earlier large native Heater Designer preview

Review geometry, material assumptions and the selected thermal/electrical model.

Manufacturing Readiness

Review fabrication findings against your manufacturer's actual requirements.

Help and upgrades

Topic	Guide
Instructions for a specific plugin	All 24 offline guides
Small panels, clipped tables or hidden options	Resize, scroll and read complete values
Missing actions, runtimes or installation paths	Troubleshooting
Dependencies and offline use	Runtime setup
Tested hosts and known limits	Compatibility
What plots, probes and analysis models represent	Analysis interactions
Command-line use	CLI guide
Repeatable reports and KiCad jobsets	Jobsets

Refresh PCM, install updates and restart PCB Editor. Keep project backups and BOM workspace files. Remove retired standalone tools to avoid duplicate actions: PDN Decoupling is in Quick PI; Return-Path Auditor and Test Point Descriptor are in Quick SI; Embed3D combines Localizer and Portable Assets.

Hardware planning details are in System requirements.

Automation and development

Use wayricad jobs for repeatable analysis/report sequences and KiCad jobsets.

Use wayricad tools list to discover all 24 command interfaces, wayricad tools doctor to check an interpreter, and wayricad tools run TOOL -- --help for detailed options. The all-tools CLI catalogue includes multi-net PI/SI studies, thermal reports and repeatable jobsets.

Developer topic	Reference
Contribution and validation requirements	CONTRIBUTING.md
Repository structure and working conventions	AGENTS.md
GUI dependencies and offline runtime setup	Runtime setup

python -m pip install -e ".[test]"
python -m pytest tests -q
python build_pcm.py --output-dir .validation/candidate-pcm
python tools/validate_packages.py --archive-dir .validation/candidate-pcm

Each plugin also has its own tests. Skipped checks do not establish native GUI compatibility. Validation records are in the release audit.

Acknowledgements and AI disclosure

WayriCAD uses AI assistance for development, research and documentation; maintainers remain responsible for validation and releases.

Project information	Reference
Maintainer	Wayri (Yawar)
WayriCAD license	GPL-3.0
Fusion and Variant Manager	MIT licensed; see each package's license
Credits and AI assistance	Acknowledgements