help.html

<!doctype html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width,initial-scale=1"><title>WayriCAD Quick PI help</title><style>body{font:15px/1.55 system-ui,sans-serif;color:#243335;max-width:1000px;margin:24px auto;padding:0 20px}img{max-width:100%;height:auto}code,pre{background:#eef2f1;padding:5px}pre{white-space:pre-wrap}th,td{text-align:left;padding:8px;border-bottom:1px solid #ddd}h1{font-size:27px}a{color:#246b88}</style></head><body>
<h1>Quick PI: inspect a DC current path</h1><p><strong>Setup and simulation files:</strong> Save setup and Load setup keep editable inputs separate from numerical results. Save simulation opens a filename and folder chooser starting in the saved PCB project directory. Load simulation accepts a chosen saved record and opens its fields, graphs, probes and time steps read-only. It does not run a solver or change the board. Matching, stale and unverified source evidence remain visible. Keep external model files with your project. Changed-board setup reuse requires explicit review; missing mappings are rejected. Reports remain separate exports.</p><p><a href="STUDY_SETUP_FILES.md">Saving and restoring AC, transient, electrothermal, multi-rail and PDN study inputs</a>.</p><p><img src="help-saved-simulation.png" width="1080" height="820" alt="Quick PI saved copper potential"><br>Public example loaded from a complete saved record. Stored values are inspected without rerunning a solver.</p><p><strong>Save complete results (updated source):</strong> Save results writes HTML, complete original numerical JSON and a portable .pocket-kivi.json companion for the matching saved PCB. Batch reports keep complete per-case companions. Keep the original JSON for reproduction; the export does not derive missing results.</p><p><b>Complete tutorials:</b> <a href="USER_GUIDE.html#marble-worked-example">Marble run</a> · <a href="USER_GUIDE.html#white-rabbit-worked-example">White Rabbit input review</a> · <a href="CONTROL_REFERENCE.html">Every control and CLI option</a>. The updated Joule checkbox opens Materials + cooling before Advanced model inputs; blank physical values remain unknown.</p>
<p><a href="USER_GUIDE.html"><b>Detailed user guide: all workflows, examples and troubleshooting</b></a> · <a href="USER_GUIDE.md">GitHub / Markdown edition</a></p>
<h2>Reviewed setup workflows</h2><p>Use <b>More → Power tree</b> for an editable energy-flow diagram with explicit converter roles, signed rails, returns and isolation. Suggestions remain unreviewed; arrows never short nets. See <a href="POWER_TREE.md">power intent</a>. Source/load and return pad pickers offer <b>Check component / same net</b>; the entered current remains the total unit current. Shared return contacts sum their mapped demands, while ordinary supply overlap remains rejected.</p><p>Use <b>Add explicit pad pair…</b> in the series editor for reviewed current terminals on multipad parts, with an explicit model; other gate/control pins are excluded. Same-component/net source, sink and component pad groups are optional; each group retains one model and total current. <a href="SERIES_PAD_GROUPS.md">Grouped-pad guide</a>. After a multi-net solve, use <b>Spacing screen…</b> with reviewed rule/material/environment inputs. A planar gap is not physical creepage. <a href="INSULATION_SCREEN.md">Screening help</a> · <a href="https://github.com/wayri/WayriCAD/blob/develop/docs/THERMAL_MATERIALS.md">Thermal materials</a>.</p>
<h2>Individual shunt capacitors</h2><p>In transient setup, select a load and open <b>Shunt capacitors for selected load…</b>. Enter each effective C, ESR and total part + connection ESL. This bank replaces aggregate C/ESR. Choose the actual return to review saved-board candidates; no part is included automatically. Unit-bearing values can prefill, while ESR, ESL and derating remain explicit.</p><p>Use a finite prescribed load-current rise for all-inductive feed/shunt paths; an ideal step needing an impulse is rejected. Quick/advanced mode and JSON retain the bank. <b>Capacitor response</b> and HTML tables select per-part internal C voltage, branch current and ESR heat; half-step differences remain evidence, not convergence proof.</p><p>Values describe a lumped ideal-return model, not extracted capacitor placement or cross-rail dynamics. Standalone prescribed-current transients only; coupled electrothermal bank stepping and converter control are unsupported.</p><img src="help-shunt-capacitors.png" width="850" alt="Native individual C ESR ESL editor with finite current rise"><img src="help-shunt-response.png" width="1000" alt="Solved selected capacitor internal voltage and branch current"><p><a href="studies/transient-shunt-bank.json">Explicit JSON example</a> · <a href="README.md#individual-shunt-capacitors-in-transient-studies">Inputs, CLI and capture provenance</a></p><h2>Connector/IC pin groups</h2><p>Select one pad. An optional <b>Include other same-net pins</b> checkbox appears only when that footprint has eligible peers on the same net. It is available for source, primary sink and additional sinks. The declared A or W is a total for one ideal equipotential group, not a separate demand for every pad. Other endpoint pins are excluded. The FEM distributes current through the declared contacts; equal sharing is not assumed.</p>
<h2>Constant-power and parallel paths</h2><p>Choose <b>Constant power · W</b> or a power-kind additional load. The operating point solves power at the actual load voltage and rejects voltage collapse. See <a href="CONSTANT_POWER.md">equations and limits</a>. This is fixed-temperature 2.5D DC; converter control, transient power regulation, shared-return power coupling, 3D, package and series-power combinations are unsupported.</p><p>The series editor detects two-pad components spanning the same net pair. Review <b>Parallel parts</b>, confirm each R/L value and select the parts to include. Highlight them on the originating PCB or review the result branches. Resistor values are suggestions; unknown DCR, capacitor and diode models are not inferred.</p>
<h2>Guided studies</h2><ul><li><a href="transient_setup_help.html">Transient setup in mΩ/nH/µF/µs</a>: enter explicit path R/L and effective C/ESR, recommend timestep, run, and review error/refinement. A matching single DC path may seed total R; avoid double counting. No L/C is invented.</li><li><a href="ac_setup_help.html">AC loop quick setup</a>: balanced conductor/return presets, explicit dimensions, DC/RMS ripple and Apply/run. The cross-section model does not infer the complete PCB or converter.</li><li><a href="decoupling/help.html">PDN capacitor-bank impedance screen</a>: declared source R/L, C/ESR/ESL, target curves, probes and CSV. Placement proximity is a separate heuristic; a sampled target pass is not board qualification.</li></ul><p>Source/sink markers are larger but translucent. In eligible current results, Ctrl+wheel near a source scales total current; near a sink marker or pad edge changes that sink unit. Close/overlapping ambiguous units leave all currents unchanged. Zoom or select a layer. Plain wheel always zooms; constant-power results require a nonlinear rerun.</p>

<h2>Live 2.5D load current</h2>
<p>After a fixed-temperature prescribed-current solve, open <b>Results</b>.
Plain wheel scrolling zooms. With <b>Ctrl+scroll load</b> checked, hold Ctrl
and wheel over solved copper to change <b>Total · A</b>. <b>Base step · A</b>
sets the normal increment. Slow scrolling uses 0.1×, normal 1×, and fast 5×.
A pause or direction reversal restarts finely. Uncheck Ctrl+scroll load to keep
wheel zoom for both gestures. The total can also be entered directly (press
Enter) or changed with its arrows.</p>
<p>All sink currents change proportionally, including multi-pad units. Voltage
drop and current density scale with current; copper loss scales with current
squared. Limits, probes, summaries and reports follow the latest completed
update. Zoom and selection stay in place. No remeshing or new factorization is
needed; calculation time excludes drawing and input scheduling. Exports wait
for pending updates.</p>
<p>Source voltage, temperature, conductivity, topology and electrodes remain fixed.
Changed simulation inputs or saved board bytes require another solve. Resistive
loads, series/package paths, coupled returns, 3D and Joule-temperature feedback
are not supported by live tuning. Use their normal Run workflow.</p>

<p><b>First-run performance:</b> fresh solves import only the needed VTK geometry filters. Multi-net batches reuse one owned board within the job, with saved-source checks for every case. Contour queries, edge bookkeeping, matrix assembly and result summaries use less Python overhead. These changes do not coarsen the mesh or loosen solver tolerances. Previous-result caching is separate. Installing missing dependencies is still an additional first-setup step.</p>
<p><a href="#workflow">Run a path</a> · <a href="#views">Previews</a> · <a href="#details">Layer details</a> · <a href="#series-editor">Series editor</a> · <a href="#board-screens">Board screens</a> · <a href="#transient">Transient</a> · <a href="#electrothermal">Electrothermal</a> · <a href="#console">Console</a> · <a href="#cli">CLI</a> · <a href="#troubleshooting">Troubleshooting</a></p>
<p>Quick PI estimates voltage drop and current flow through saved traces, filled zones, pads and plated via barrels. The default <b>2.5D · layered copper</b> model solves DC conduction locally and leaves the PCB unchanged. To solve copper volume, choose one net, two distinct pads and a specified sink current; select <b>3D · copper volume</b> under Copper model, then click <b>Run 3D</b>. The first run prepares Gmsh in the private runtime if necessary. Use Mesh &amp; material to set mesh edge, assumed via plating, fixed copper temperature and the tetrahedron budget. The result window has board top and 3D views, layer/via filtering, current density, voltage and loss density. Plotted cells are sampled for speed; exported JSON includes the complete mesh and field. CLI <code>--model-dimension 3d</code> runs the same model. These copper modes do not solve AC fields, transient inductive behavior or thermal feedback. Separate studies provide explicit lumped R/L/C transients and electrothermal coupling. Regular layer maps remain 2.5D; the 3D export provides a separate interactive HTML view and complete JSON.</p>
<h2>Responsive board view and saved silkscreen</h2><p>The board context shows saved, visible silkscreen with native size, position and rotation. Hidden fields stay hidden. Fabrication and courtyard drawings are not part of this default view. References are not invented at component centres. Source/load markers remain; inspect their pad details in the sidebar. Scientific report plots retain their source/load captions.</p><p>Dragging pans a cached image; releasing redraws the exact view. Redraw requests are coalesced, and hover probes use nearby geometry with exact containment checks. Moving within the same sampled cell does not redraw the board.</p><img src="help-native-viewport.png" alt="Native Quick PI window displaying physical silkscreen on the public Marble board"><p>Development preview using a saved illustrative +3.3P result on Marble, with a 3.3 V source and assumed 0.2 A load. This is a source-window check, not a measured board or an installed-editor qualification.</p><h2>First-open copper</h2><img src="help-first-copper.png" alt="Actual Marble +12 V copper on all projected layers with Silk disabled"><p>Read-only saved geometry preview on public Marble; no mesh or electrical result is calculated.</p><p>Saved copper loads in the background with the net and pad inventory, without requiring solver stackup or terminal inputs. The selected net opens with All copper layers (projected) selected and Silk off; net changes filter the cached board. Turn off Only simulated nets for surrounding copper, or select All copper layers (projected) for a combined view. Board retains edges and holes; Silk separately enables saved silkscreen. Copper and Field control geometry and the result overlay. Preview prepares simulation geometry; Run solves it. Initial copper display is not an electrical result.</p><h2>Board-first workspace</h2><p>Setup and Details start closed so the board gets the window width. Setup holds nets, source/sink pads, loads and mesh controls. Details contains layers, colours, sortable tables and probes. Focus view hides both drawers and restores their prior widths on the next click. Run and Files remain visible; Files provides setup/result Save and Load plus report export. The header retains the current field name, limits and units.</p><p>Current tuning starts folded. Open it for numeric current and step controls; Ctrl+scroll on solved copper or a sink still works with it folded. Ordinary scroll zooms. Fit or double-click restores the complete board. Geometry is never stretched to fill the window.</p><img src="help-viewport-first.png" alt="Quick PI board-first workspace on an illustrative synthetic power board"><p>Native 1280 × 800 Windows/KiCad window. Public synthetic plate field and disposable PCB context; no private board, measurement or hardware validation is implied. <a href="VIEWPORT_LAYOUT.md">Layout evidence and gestures</a>.</p><h2>Board workspace</h2><p>The window opens maximized. Setup on the left holds the net, pads, source and load inputs, with Preview, Run, Export and Series at the bottom. Details on the right holds the layer, result, calibrated colour range and exact probes. The board uses the full height between the compact header and status line, without graph axes.</p><p>Click Setup or Details in the header to hide either side panel. Drag to pan, use the wheel or + / − icons to zoom, and double-click or click Fit to restore the whole board. A millimetre ruler shows the current scale. Board, Copper, Field and Silk independently control board edges/holes, extracted copper, the result overlay and optional saved silkscreen. The save-image icon exports the visible board canvas. Mesh &amp; material, Console and Model details start folded; expanding them scrolls the sidebar. More contains transient, electrothermal and diagnostic studies.</p><img src="help-workspace.png" alt="Compact native Quick PI workspace on a disposable portrait PCB"><p>UI demonstration: a uniform 65 × 90 mm, 35 µm copper plate with full-height edge contacts at 5 V / 2 A gives 0.71149 mV. The saved PCB is context for this analytical fixture; its illustrated traces are not the solved plate model. This is not a measured-board result.</p>
<p>Large planar exports (more than 100,000 triangles or at least 250 extracted vias/PTHs) generate three static maps: drop or ground rise, current density, and copper loss density. They use Solver cells style and preserve all plotted cells, copper and drill contours without sampling. Dense patches are batched and figures are released between maps. Three interactive fields and complete numerical JSON remain available. For all seven static maps, set <code>"report_options": {"extended_snapshots": true}</code> on the result bundle passed to <code>write_report</code> or <code>write_batch_report</code>; batch options apply to children. There is no CLI flag for this export option. Small exports retain seven maps. Batch DC/return child JSON files are evidence descriptors with source custody, scalar summaries and exact pointers into the complete parent batch JSON. Shared-return descriptors declare the potential/current sign transforms used for physical maps. Keep the parent JSON beside the case-report folder; child descriptors are not standalone numerical results. Original arrays remain complete in the parent archive. Standalone reports retain full paired JSON; batch publication uses the optional evidence_reference keyword of write_report to avoid duplicating arrays.</p>
<h2 id="batch">Multiple nets, return copper and Joule feedback</h2>
<ol><li>Choose an explicit source and load on one net, then open <strong>Rails / ground returns…</strong>.</li><li>Use <strong>Add net case…</strong> for every additional rail. Choose its net, source and load pads; enter the voltage and current. The saved-pad catalogue helps resolve labels.</li><li>To calculate return copper drop, enable <strong>Solve explicit DC return copper</strong>. Choose the return net, then the load-ground pad where return current enters and source-ground pad where it leaves. No ground net is chosen automatically.</li><li>Review the visible case JSON, then <strong>Run all cases</strong>. Results retain failed cases; changing inputs disables export until rerun. Export HTML/JSON for the comparison and individual evidence.</li></ol>
<p>CLI: <code>wayricad-pi board.kicad_pcb --batch cases.json --output raw-cases.json --html cases.html</code>. Start from <a href="studies/batch-rails.example.json">the example study</a> and replace its illustrative nets, pad labels and load values. Batch studies contain 1–32 cases tied to one saved-board hash. Explicit shared-return groups calculate common copper DC coupling at fixed current and temperature; other cases remain independent. They do not calculate AC electromagnetic coupling or shared multi-rail heating.</p>
<p><strong>DC always includes I²R loss.</strong> Checking <strong>Include Joule heating / temperature feedback</strong> makes Run open a steady coupled-study setup. Enter the missing thermal conductivity, cooling coefficient, emissivity, ambient, material temperature range/cap, resistivity at 20 C and temperature coefficient. Unreviewed null values block solving. Delivered load power is not automatically heat in the PCB.</p>
<p>An explicit fixed-temperature return loop combines supply/return resistance, drop and copper losses. Load voltage is source voltage minus both path drops. One prescribed-current load and 2.5D linear copper are supported. For multiple loads or rails, use a shared-return group. Package/series paths, resistive loads, full 3D loops and loop thermal feedback are unsupported in shared-return groups. Return plots retain a declared auxiliary voltage reference and give the offset to source-ground zero. The separate Return path geometric audit does not calculate loop voltage drop, inductance or AC impedance.</p>
<p>CLI exits: 0 completed, 3 incomplete/failed/review required, 4 infeasible, 2 intake/execution/publication error. Use different files for --output JSON and the HTML paired JSON.</p>
<h3>Multi-pad units and shared return copper</h3><p>In <strong>Rails / ground returns…</strong>, choose <strong>Edit source / load pad units…</strong>. Select a rail and its source or load unit, then select all pads on that net. For a load, enter a stable ID and its total current. Pads within each unit are explicitly ideal equipotential contacts; FEM divides the current according to copper conductance, without an equal-current assumption. Different units cannot overlap. This does not model package/contact resistance.</p><p>Choose <strong>Add shared return group…</strong>, select the participating rail cases, the return net, source-ground pads, and ground pads for every load. The common return mesh is solved once with all injected currents. Results show each load's ground rise and delivered supply voltage, shared copper loss counted once, and power/current checks. Shared return maps show physical ground rise/current direction. JSON retains auxiliary reversed-current FEM evidence and its sign convention. Use one group per return net; combine loads sharing a supply net in one case. Every participating supply load needs a stable ID and exactly one return mapping. Cases outside groups remain independent.</p><p>CLI uses the same <code>--batch</code> command. See <a href="studies/shared-return.example.json">the illustrative shared-return study</a>: <code>source_terminals</code>, load <code>terminals</code> and <code>current_A</code>, and top-level <code>shared_returns</code> with <code>case</code>/<code>sink</code>/<code>terminals</code> mappings. Replace every example pad/current with reviewed inputs. Shared groups support fixed-current 2.5D copper at fixed temperature; regulator feedback, AC fields, package/series paths, resistive load solving and joint thermal feedback are unsupported.</p>
<h2 id="workflow">First run</h2><ol><li>Refill zones and save the originating PCB. Open Quick PI from that PCB Editor.</li><li>Choose one net, a source and primary sink pad. Set source voltage and sink current. Add further loads with Additional sinks and optionally set Limit · A.</li><li>Click Run in Setup, then inspect Net, Mesh and Results. Select the desired layer and quantity.</li><li>Open Losses in the inspector for sink voltages/limits, source feasibility and numerical details.</li><li>Export report for offline HTML maps and paired JSON containing every layer and result.</li></ol>
<h2>Multiple sinks and source current budget</h2><p>The primary sink uses Load · A, Min · V and Max · V. Additional sinks opens an editable table for other distinct pads on the same net, with current demand and optional voltage bounds. Use Add sink, Update selected or Remove selected, then OK to apply. Blank minimum defaults to 0 V; blank maximum is unbounded. The source pad cannot be a sink.</p>
<p>Limit · A is a nonnegative current budget; blank means unlimited and zero supplies no current. All constant-current demands are solved together at the set source voltage. FEASIBLE means total demand fits the source budget and sink voltages meet their bounds. It does not establish thermal, transient or hardware qualification. INFEASIBLE identifies failed requirements and retains source current headroom and each sink's diagnostic voltage/drop.</p>
<p><strong>Source overload maps are requested-load diagnostics.</strong> A source whose current limit is below demand cannot sustain the calculated operating point. The tool does not scale loads, simulate regulator foldback or solve voltage-collapse dynamics. Worst drop / total demand and the multi-sink drop/current map are diagnostic normalizations, not physical two-terminal resistance. Changes to any load or bound clear old results. Additional sinks and explicit console series components cannot be combined; the single-sink series path still accepts the visible source current and sink voltage limits.</p>
<img src="help-workflow.png" width="860" alt="Earlier native Quick PI results with actual saved layer thickness">
<p><strong>Screenshot scope:</strong> Berkeley Marble's small <code>Net-(R161-Pad1)</code> connection, <code>U1.M6</code> to <code>R161.1</code>, at 1 V / 1 A. This is not a power-rail or full-board loading test. Computed drop is about 2.568 mV: 0.652 mW in sheets and 1.916 mW in via barrels. It is a regression result, not a physical measurement or mesh-convergence certificate.</p>
<h2 id="views">Inspect the same copper in three views</h2><table><tr><th>View</th><th>Purpose</th></tr><tr><td>Net</td><td>Check actual copper, terminals and drill holes before interpreting results.</td></tr><tr><td>Mesh</td><td>Inspect triangle resolution, narrow necks and contact boundaries.</td></tr><tr><td>Results</td><td>Choose absolute voltage, drop, current density, current-flow arrows, loss density, pulse screen or DC drop/current.</td></tr></table>
<img src="help-net.png" width="860" alt="Actual extracted copper and terminals on the small Marble net">
<img src="help-mesh.png" width="860" alt="Corresponding finite-element mesh on the selected layer">
<h2 id="transient">Transient load steps and decoupling</h2>
<p>Open <strong>More → Transient load-step study</strong>. Set the shared source R/L, each load-path R/L, local capacitor C/ESR, before/after current and step time. Capacitance and shared source resistance require explicit entry; no L/C is inferred from PCB geometry. Units are SI: 100 µF is 100e-6 F. Run transient opens raw voltage/current time plots and Checks / limits. Export HTML / JSON retains all inputs and samples. Input or saved-source changes require a new run.</p>
<p>The separate lumped network starts in pre-step DC equilibrium and uses backward Euler with a half-step comparison, charge and energy accounting. Exact event timestamps retain before/after samples for ESR jumps. Refine the time step to assess waveform accuracy. Source current limits remain budget diagnostics; no regulator CV/CC, foldback or control loop is simulated. These are load-node traces, not transient PCB field maps. Use the <a href="studies/transient-load-step.json">illustrative input</a> with <code>wayricad-pi --transient transient-load-step.json --html pi-transient.html --output pi-transient-data.json</code>; replace its values with your actual circuit. An optional positional PCB supplies saved-file provenance only. Exit 4 reports a limit violation.</p>
<h2 id="electrothermal">Electrothermal feedback</h2>
<p>Open <strong>More → Electrothermal study</strong>. Choose <strong>Steady saved-board coupling</strong> or <strong>Transient lumped coupling</strong>. The explicit model editor starts from the selected electrical settings. <code>null</code> marks a missing physical input. Load study JSON, review its materials, cooling and heat mappings, then Run electrothermal. Coupled results shows sink voltages and temperatures; Checks and solve actions retains convergence, energy balances, limits and reasons for a stopped solve. Changed inputs clear old results. Cancel run discards partial work.</p>
<p>Steady coupling needs a saved explicit stackup, closed Edge.Cuts, dielectric/copper conductivity, via plating, convection/emissivity and a reviewed material temperature range. Planar and via Joule losses heat matching thermal cells; the returned conductor temperature changes local copper resistance. Cold/hot voltages and raw layer fields are retained. Explicit series branches require contact polygons; their resistance remains fixed in this mode. Delivered load power is not automatically PCB heat. Missing cooling, uncovered sources or unsupported narrow grid geometry block the solve with a diagnostic.</p>
<p>Transient coupling needs explicit source/path R/L, C/ESR, thermal R-theta (K/W), C-theta (J/K), initial temperatures and power steps. Map each nonzero resistor exactly once to a thermal node and declare its reference temperature/coefficient and validity range. Electrical and thermal states persist across accepted intervals. Only resistive dissipation heats nodes; reactive storage and numerical damping do not. Review both integration and exchange refinement checks. This is a lumped model, not a spatial transient field.</p>
<p>Export HTML / JSON retains assumptions, source/study hashes, raw results and checks. Changed saved sources block export. Source current budgets remain diagnostic; no CV/CC or foldback is simulated. Temperature caps, invalid material ranges and exhausted coupling iterations produce no valid hot operating point. Quick PI vendors the shared QuickTherm kernels and works independently of a QuickTherm installation. Steady coupling rejects unplated drilled holes, plated slots and backdrills; plated drill-core cavities remain unresolved by its uniform-grid approximation. See <a href="ELECTROTHERMAL.md">complete model and CLI reference</a>, <a href="studies/electrothermal-steady.json">steady example</a> and <a href="studies/electrothermal-transient.json">transient example</a>. CLI: <code>wayricad-pi --electrothermal study.json --html coupled.html --output coupled-data.json</code>; optional positional PCB supplies saved-board geometry when the study uses <code>electrical</code> selections. Exit 3 means incomplete coupling; exit 4 means an operating limit violation. Illustrative examples are assumed models, not measured-board validation.</p>
<h2>Continuous field display</h2>
<p><strong>Smooth gradient</strong> is the default result display and stays continuous when zooming. Voltage, drop and transfer resistance use the linear solved nodal field. Density, flow, loss and pulse risk use area-weighted cell interpolation for display within the same layer and copper thickness. Holes, disconnected islands and unavailable cells remain uncolored. Probes, hotspot rankings and automatic scale peaks retain solver values. Choose <strong>Solver cells</strong> to inspect the original cell resolution. Smoothing does not refine the analysis mesh; exported maps and JSON retain the display choice.</p>
<p>Drag to pan, scroll to zoom and use Fit to restore the extent. More → Zoom to circuit terminals focuses the chosen pads. More → Refine mesh and rerun halves the edge length. Compare resistance and peak density across refinements; localized peaks can remain sensitive after total resistance stabilizes.</p>
<p>Managed launches prepare Gmsh automatically when its backend is explicitly selected, including in batch rails, independent returns and shared-return groups.</p>
<p>With the optional Gmsh Python package installed in the Quick PI runtime, extracted planar copper and contact regions use a conforming Gmsh mesh. Otherwise the VTK mesher runs. Both feed the same 2.5D DC solver, and the mesh report records the backend. The CLI accepts <code>--mesh-backend gmsh</code> or <code>--mesh-backend vtk</code> to require either backend.</p>
<p>The default 2.5D copper budget is 400,000 triangles across all layers. For a dense net, explicitly choose <code>--max-cells 1500000</code>, or set <code>"max_cells": 1500000</code> in a batch case's <code>electrical</code> settings or a <code>shared_returns</code> group using the advanced JSON editor. Each case/group has its own total budget. Values must be integers from 1,000 to 2,000,000; enlarged solves also retain a 2,000,000-vertex ceiling. Several GB of memory and longer execution may be needed. Edge length, contours, holes, area and conservation checks remain enforced. Series/package paths retain their existing limits; 3D uses its separate tetrahedron budget.</p>
<p>Resize the divider to give the copper viewport or inspector more space. Board context, copper geometry and the result overlay can be switched independently. Context comes from the actual saved board geometry; it is display-only and does not expand the solved electrical scope.</p>
<p>The inspector ranks local current density and volumetric heating under <strong>Hotspots</strong>. Select a row to switch layers, mark the solved location and zoom there. Click solved copper in Results to inspect the containing triangle or plated barrel under <strong>Probe</strong>. Empty space and drill holes have no copper result. Heating rankings use W/mm³; the loss map uses W/mm². These are mesh cell/barrel estimates, not whole-track measurements. Losses retains thickness and loss accounting.</p>
<p>Choose an automatic scale for the selected layer, a shared scale across all solved layers, or manual limits in the displayed units. Minimum must be below maximum; changing the metric resets manual limits. A manual range can clip values. Exported HTML/JSON retain the chosen scale mode.</p>
<p>Select object in PCB navigates only through exact saved object identities where available; Select source and all sinks in PCB selects the reviewed pads. Read PCB selection brings a selected track, pad or via into the inspector. Objects outside the current DC model show no invented electrical values. A local mesh cell index is not a KiCad UUID. Saved-file changes block navigation/export until reload and rerun; live unsaved changes are outside the saved analysis snapshot. These layer-map results remain 2.5D DC conduction with the documented contact, material and mesh limits.</p>
<h2 id="details">Thickness, loss accounting and hotspots</h2><p>Copper thickness comes from each saved stackup layer, not a nominal copper-weight guess. It controls conductance and copper thermal mass. Missing or ambiguous stackup data stops the run. Via plating defaults to an assumed 25 µm and is separately configurable.</p>
<img src="help-layer-details.png" width="860" alt="Native layer thickness, volume, sheet and via losses, and ranked hotspot coordinates">
<p>The detail window lists layer area, volume, connected area, thickness and peak current density, then ranked local heating hotspots with XYZ locations. Sheet, via-barrel and component losses are separate. Floating copper remains in geometry area but has no connected loss result. The HTML report includes these details.</p>
<p>For one sink, ΔV/I is the solved path resistance for linear copper/RL paths; for multiple sinks, worst drop / total demand is a diagnostic ratio. With a diode or fixed drop it is an apparent ratio at the requested current, not resistance. Source V/I describes the operating point and is not copper resistance. Sheet current is A/mm; current density is A/mm². The pulse screen compares deposited energy with energy to reach the entered temperature limit without cooling. A ratio above one is not a fuse-time prediction. Heat spreading, temperature feedback, melting and fuse-opening physics are excluded.</p>
<section id="ac-smps"><h2>AC / SMPS copper study</h2><p>The current development workflow starts with a quick loop and live return preview. Run applies the visible recipe. Custom conductor/spectrum and mesh controls start folded. Results use summary cards and one large selectable chart; kHz, mΩ and mW replace long raw decimals. Drag the plot/table divider to resize. <a href="ac_setup_help.html">Step-by-step AC guide</a>.</p><img src="help-ac-setup-3.6.40.png" alt="Simplified native AC quick-loop setup"><img src="help-ac-impedance-3.6.40.png" alt="Large discrete 100 kHz impedance chart and readable engineering units"><p>Choose <strong>More → AC / SMPS copper study…</strong>. This separate straight-section cross-section model uses explicit copper geometry, return conductors, mean DC current and RMS current per ripple/switching harmonic. It calculates frequency-dependent copper current redistribution and Joule losses. It does not turn a DC board field into an AC field.</p><p>For an SMPS, obtain harmonic currents from a reviewed circuit simulation or measured waveform. The study does not simulate switching devices, control loops, magnetic cores, capacitors or arbitrary routed-board AC fields. Rail voltage provides context; it does not qualify HV creepage, clearance or insulation. A high-current copper-loss calculation does not establish a safe temperature.</p><p><a href="AC_ANALYSIS.md">AC inputs, equations, CLI and applicability</a>. Ordinary DC already calculates I²R loss. The <strong>Include Joule heating / temperature feedback</strong> checkbox adds the existing steady saved-board DC thermal/resistivity iteration, with explicit material and cooling inputs. AC harmonic loss is reported separately; it is not silently injected into that thermal solve.</p></section>
<h2 id="series-editor">Native series editor and operating point</h2><p>Choose <strong>Build series path…</strong> to select source and sink pads and add compatible two-pad components in order. You can import one or two selected pads from the PCB Editor that launched Quick PI. Confirm their source-to-load order. Each component needs an explicit resistance/RL, fixed drop or diode model; the editor checks saved-net continuity and can save or load its JSON path.</p><p>The default mode prescribes current. <strong>Resistive load</strong> solves a positive DC current from source voltage, path losses and an entered load in ohms. <strong>More → DC current sweep</strong> plots path drop and sink voltage over 2–200 positive, prescribed currents. These are fixed-temperature DC calculations, not waveforms or electrothermal feedback.</p>
<h2 id="board-screens">Return path</h2><p>Choose a routed signal and its real return net(s). Refill zones and save first. The view marks sampled gaps in adjacent filled copper and checks for selected return vias near evidenced layer transitions. A clear screen cannot prove current flow, impedance or plane continuity. <a href="RETURN_PATH.md">Method and limitations</a>.</p>
<h2 id="console">Console and explicit series components</h2><p>Expand Console. Use <code>help</code>, <code>nets</code>, or <code>pads &lt;net&gt;</code>. Tab cycles completions; Up/Down recalls commands. This is a bounded command interface, not Python or a shell.</p>
<pre>run pi "Net-(R161-Pad1)" U1.M6 R161.1
run pi U1.M6 R161.1 5m R161.2 U1.M5
run pi U1.M6 R161.1 5mH+30m R161.2 U1.M5
run pi VIN.1 D1.1 1V D1.2 LOAD.1
run pi VIN.1 D1.1 diode(Vf=0.7V,Iref=1A,n=2,T=25C) D1.2 LOAD.1</pre>
<p>Values in the last two examples are explicit user assumptions for that component: 5 mΩ, or 5 mH plus 30 mΩ. They do not identify the actual fitted R161 automatically. Inductance adds no steady-state DC voltage drop; stored magnetic energy is reported. Component links are dashed, not invented PCB tracks. Source voltage/current and material settings use the visible controls.</p>
<p>Engineering notation supports milli <code>m</code>, mega <code>M</code>/<code>Meg</code>, <code>u</code>/<code>µ</code>, <code>n</code>, <code>p</code>, scientific notation, and explicit H/ohm/Ω units. Pads such as C1.1, U8.2 and Q2.3 must resolve unambiguously.</p>
<p><code>1V</code> or <code>500mV</code> gives a deterministic forward drop. <code>diode(...)</code> evaluates an ideal diode equation at the specified DC load current using a user-entered Vf/Iref anchor, ideality n (1–4), and temperature in °C. Choose the two pads in forward source-to-load order. Each result includes current, forward drop, voltage before/after and power. No fitted component model is inferred. Prescribed-current mode does not infer current from source voltage; resistive-load mode does. Neither solves reverse bias or an instantaneous waveform. If the requested current would leave a negative sink voltage, the UI warns that the operating point may be infeasible. Forward-drop paths must cross each net once so the selected part has no alternate bypass path.</p>
<h2 id="cli">Command line</h2><p>Install the suite wheel for <code>wayricad-pi</code>. From a source checkout use <code>python -m quick_pi_plugin.cli</code> instead.</p>
<pre>wayricad-pi --help
wayricad-pi board.kicad_pcb
wayricad-pi board.kicad_pcb --net "Net-(R161-Pad1)" --source U1.M6 --sink R161.1 --voltage 1 --current 1 --mesh-edge 0.5 --pulse 1 --temperature-limit 150 --html pi.html
wayricad-pi board.kicad_pcb --command "run pi U1.M6 R161.1 5mH+30m R161.2 U1.M5" --html series.html
wayricad-pi board.kicad_pcb --net +3V3 --source J1.1 --voltage 3.3 --source-current-limit 2 --load U1.1 0.8 --load U2.1 0.6 --load-voltage-limits U1.1 3.1 3.4 --load-voltage-limits U2.1 3.0 - --html multisink.html</pre>
<p>Repeat <code>--load PAD CURRENT_A</code> instead of <code>--sink</code>/<code>--current</code>. Optional <code>--load-voltage-limits PAD MIN_V MAX_V</code> applies to a matching load; use <code>-</code> for an omitted bound (minimum defaults to 0 V; maximum is unbounded). <code>--sink-min-voltage</code>/<code>--sink-max-voltage</code> set bounds for legacy single-sink or series <code>--command</code> paths. <code>--source-current-limit</code> accepts a nonnegative ampere budget and also works with legacy single-sink/series paths. <code>--load</code> cannot combine with <code>--sink</code>, <code>--current</code> or <code>--command</code>. Exit 4 means the source budget or a sink voltage requirement is infeasible, and takes precedence over convergence status. Diagnostic results and reports remain available.</p>
<p>The board-only command lists nets/pads/layers. Replace sample names with those on your board. Mesh edge and plating are mm; pulse is seconds; temperatures are °C. Without a CLI pulse duration, thermal screening requests one. HTML requires a completed solve, sweep or return-path review. Exit 0 means execution succeeded, not that the electrical design or convergence passed.</p>
<p>Triangle-angle improvement preserves copper, holes and terminal boundaries. Broad complex planes receive interior mesh points to reduce unnecessary subdivision. Geometry and conservation checks and the mesh-size budget remain enforced. Compare resistance and localized current density separately across refinements.</p><h2 id="troubleshooting">If a run fails</h2><table><tr><th>Problem</th><th>Action</th></tr><tr><td>Missing stackup</td><td>Save explicit copper/dielectric thicknesses in Board Setup.</td></tr><tr><td>Unfilled zones</td><td>Refill and save in KiCad.</td></tr><tr><td>Disconnected terminals</td><td>Check pad/net selection, actual copper continuity and filled contacts. Cross-net paths need explicit series components.</td></tr><tr><td>Mesh budget or timeout</td><td>Use a larger mesh edge or smaller net, then refine gradually.</td></tr><tr><td>Dependency setup</td><td>Read the reported setup log; check KiCad 10 Python and package-mirror/proxy/offline-wheel configuration.</td></tr><tr><td>Wrong/stale project</td><td>Save and launch from the intended PCB Editor. Each action retains that editor's IPC connection.</td></tr></table>
<p>All screenshots and help assets are bundled locally. Numerical dependencies are prepared in a private user cache; the first setup may need network access. A complete KiCad 10 installation is required. KiCad 11 live operation is not certified.</p><h2>Decoupling placement</h2><p>The Decoupling placement tab incorporates PDN and Decoupling Planner: rail/ground/load patterns, capacitor qualification, proximity checks, regulator candidates, placement map and CSV findings. It uses the same saved board; More → Reload saved board refreshes it. These placement heuristics do not constitute AC PDN simulation and do not move components. <a href="decoupling/help.html">Detailed placement help</a>.</p><img src="help-decoupling.png" alt="Native integrated decoupling map on a disposable load/capacitor board"><h2>Zoned power-rail example</h2><img src="help-power-rail.png" alt="Marble MGTAVCC voltage drop, zoomed to In7.Cu"><p>Actual copper from L34.2 to U1.C6, with a hypothetical 1 A single-pad sink: the pictured 0.5 mm mesh gives 2.520 mV. Refinement to 0.0625 mm gives 2.657 mV. The final drop change is 0.573%, but the preceding step and sheet-loss stability fail the two-step 1% criterion. Peak current density remains unconverged. This is not a distributed FPGA-load or regulator model.</p><h2>Verify numerical accuracy</h2><p>Run <code>wayricad-pi --verify --output pi-reference-results.json</code> for eight known-answer cases: straight/parallel conductors, a plated via, the published Elmer beam/circuit operating point and radial annulus refinement. Passing these verifies those models; it is not a measured-board validation.</p><h2>Mesh convergence</h2><p>Choose <strong>More → Check mesh convergence</strong> for 3–5 meshes, halving the requested edge at each step. Both final steps must meet the tolerance (default 1%) for drop, resistance, total and sheet loss, with conservation checks. The plot separates terminal drop from local current peaks. Budget/geometry failure means INCOMPLETE. Peak-current and fusing-risk convergence remain unverified.</p><img src="help-convergence.png" alt="Native mesh refinement plots and conservation criteria"><p>CLI: add <code>--converge-levels 4 --convergence-tolerance-percent 1</code> to a solve. JSON and HTML retain the study; exit 3 means incomplete or not stable, exit 2 means execution failed. A stable result is not a rigorous error bound.</p><h2>Automatic reports and KiCad jobsets</h2><p>Install the WayriCAD CLI wheel alongside the GUI plugins. In the saved project folder, run <code>wayricad jobs init --preset inventory</code>, then <code>wayricad jobs run --keep-going</code>. Reports, logs and a linked HTML summary go into a fresh <code>reports/wayricad/</code> run folder. Inventory lists available nets and paths; choose the electrical preset and explicit terminals for numerical analysis.</p><p>Use <code>wayricad jobs jobset --output analysis.kicad_jobset</code> to create a native KiCad jobset. Use <code>--merge existing.kicad_jobset --position 1</code> to insert into an existing sequence, writing a new file. Open the resulting jobset in KiCad's Jobsets manager and run it. Nonzero tool exits and missing reports fail the sequence; successful execution is not engineering approval. <a href="https://github.com/wayri/WayriCAD/blob/develop/wayricad_runtime/JOBSETS.md">Complete setup, presets and automation guide</a>.</p><section id="interactions"><h2>Net picking, cursors and probes</h2><p><strong>Find net</strong> uses a case-insensitive literal substring by default. Use <code>*</code> and <code>?</code> for wildcard matches; square brackets are literal KiCad bus punctuation, so <code>DATA[0]</code> selects one bit and <code>DATA[*]</code> searches bus bits. Prefix a query with <code>~</code> for opt-in typo-tolerant ranked suggestions. Typing only filters the list: it does not create a net or replace the selected net, which stays pinned if it does not match. <strong>Pick net</strong> lets you click a saved pad, track or via. Choose the terminals and rerun after input changes.</p><p>Hover over Results cells to read exact values; click to pin, and Ctrl-right-click to clear. Missing cells and holes remain gaps. The 3D copper dialog supports orbit, pan, wheel zoom and sampled-cell probes. <strong>Export 3D report</strong> writes an offline interactive HTML view and complete JSON. HTML controls: drag to orbit, Shift-drag to pan, wheel to zoom, Fit to restore, click to pin and Clear probes to remove pins. This moves the display only; the PCB and solver are unchanged. Planar reports provide interactive maps alongside static print figures.</p><p>The 3D display is sampled solved copper, not STEP component solids.</p><p><a href="https://github.com/wayri/WayriCAD/blob/develop/docs/ANALYSIS_INTERACTIONS.md">Full view and probe guide</a>.</p></section><h2>Explicit package contacts</h2><p>Setup → Package contacts enters physical lead, solder and BGA paths for 2.5D constant-current DC. Each path binds one reference/pad/optional UUID and explicit copper layer to a package port: source or sink:&lt;selected sink pad UUID&gt;. CLI --package-conduction paths.json also accepts sink:&lt;exact requested terminal label&gt;. Several contacts may share a port; currents are solved from the network, never prescribed per ball.</p><p>Enter explicit geometry and resistivity for every ordered series segment: cylinder (length, diameter), rectangular (length, width, thickness), or symmetric truncated spherical_ball (length strictly below diameter). Dimensions are mm; rho_ohm_m is Ω m. No material/dimension defaults are inferred. A contact attaches only to its declared copper face; PTH barrel conduction remains finite. Ambiguous, duplicate, overlapping or cross-net attachments fail.</p><p>Results show current, drop, I²R and package/board voltages per contact, plus separate sheet/barrel/package loss conservation. Source and sink voltage limits include the contacts. Ports without paths retain legacy ideal terminals. These are axial 1D paths coupled to board FEM, not 3D package fields. Explicit contacts are unsupported in 3D, series, resistive-load, sweep, rail-transient and electrothermal studies. See README for the JSON schema and evidence requirements.</p><section><h2>Explicit return nets and terminal declarations</h2><p>Choose the actual return nets with the searchable multi-select Find… control. Optionally select the source and load/receiver return pads; these are declarations, not a solved current loop. Quick PI provides the Return path tab; Quick SI adds an optional Explicit return-path review.</p><p>The review covers the whole signal net. Inspect sampled reference coverage, observed signal-via routing layers, reference nets/layers, and nearby return vias with their distances, spans and sampled copper contact. Proximity alone is not continuity; mismatched return nets and missing contact evidence stay unresolved. Filled-zone geometry does not establish return resistance, inductance or current distribution. Save and refill zones before rerunning after edits. Exported HTML retains detailed evidence tables.</p></section><h2>Selection and changing inputs</h2><p>Read PCB selection retains all selected copper for highlighting and expands selected component pads; the numeric inspector describes its primary item. Add to existing PCB selection extends the editor selection. Changing inputs cancels an active job and discards late results. Navigation does not edit copper or certify unsaved geometry.</p>
<section><h2>Resize and read the workspace</h2><p>Drag the Setup divider to widen inputs and the Details divider to widen result details. Expanded Mesh &amp; material and Console sections scroll. Hide and reopen either sidebar to give the board more room without discarding inputs.</p></section>
<section><h2>Source-to-sink power flow</h2><p>After a solve, click <strong>Power flow</strong> (or <strong>Power flow…</strong> in Multi-net cases) to open an offline Sankey diagram. Source units are on the left, delivered load power and modeled losses on the right. Hover or click a ribbon to inspect watts. HTML exports, including CLI <code>--html</code>, include the same diagrams automatically.</p><p>Each multi-pad unit counts once at its solved total current. Shared-return studies pool their sources and count common return loss once; they do not invent a per-rail allocation. Independent loop budgets include supply and return losses. Standalone rail budgets include only their modeled path. These are power-accounting diagrams, not current streamlines or automatic conversion of load power into board heat. Additional loads in large lists are combined with their power retained.</p><p>Missing or inconsistent evidence shows an unavailable explanation. Infeasible requested-current results stay labelled diagnostic. A return-only ground-referenced solve must be viewed in the coupled study for a physical source-to-load budget. Steady electrothermal exports show cold and hot budgets separately, with their acceptance status; a DC Sankey cannot represent transient stored energy.</p></section><section><h2>Automatic mesh sizing</h2><p><strong>Automatic mesh</strong> is enabled for 2.5D. Preview saved copper to review recommended background and local sizes in the inspector. Run uses a graded local size field near straight tracks, pad-contact bounding boxes and barrel lands. Uncheck Automatic mesh to edit the preserved manual edge; 3D automatically switches to manual sizing.</p><p>The background starts at occupied copper extent / 40, capped at 0.8 mm. Its area-based estimate reserves 75% of the cell budget for features and boundaries. Local widths target three edges across a feature; target size grows gradually with distance. Shared edge splits preserve conforming contacts, copper contours and holes. The exact resource guard can still reject complex geometry; feature targets are never silently coarsened.</p><p>Use CLI <code>--auto-mesh</code>, or JSON <code>"mesh_sizing": "auto"</code>. Manual <code>--mesh-edge</code> and <code>--auto-mesh</code> cannot be combined. Batch supply and return settings accept the same key. Old requests retain manual sizing. Reports record chosen and ideal sizes, actual counts, budgets, achieved edge/target ratios and unresolved features.</p><p>This is not a numerical error estimate. Arc contours, arbitrary zone necks and contact singularities require separate review. A convergence study fixes the initial recommendation, then halves uniform manual edges; Refine also selects a manual half-edge mesh. Neither action silently repeats the same automatic recommendation.</p></section><h2>Faster selection and focused maps</h2><p>Search with text, * or ? wildcards, or ~text for fuzzy matching. Bus brackets are literal. Filtering keeps the chosen net and current result until you explicitly choose another net.</p><p><strong>Only simulated nets</strong> is enabled by default and also applies to exported maps. Turn it off to inspect surrounding copper. <strong>Select simulated nets in PCB</strong> replaces the PCB selection with exact net copper across all layers.</p><p><strong>All copper layers (projected)</strong> overlays the layer fields without summing or averaging them. At overlapping solved copper, click and choose the layer to inspect. Report probes identify each cell's layer; use an individual layer to avoid visual occlusion.</p><p>Native display extraction runs in the worker, and unchanged display paths and plots are reused. Source changes still require reloading and rerunning.</p><section id="copper-melting"><h2>Copper melting and bottlenecks</h2><p>After a 2.5D solve, choose <strong>Copper melting bottlenecks</strong> in Inspect or the <strong>Pulse / adiabatic melting action</strong> map. Select a ranked row to focus the actual solved cell/barrel, highlight its saved native object when identified, and use Select to navigate in PCB Editor. Blue B1–B6 markers on density/melting maps locate ranked regions. HTML reports include the complete table, markers and material inputs; large reports render the melting map when extended snapshots are requested. CLI JSON and summaries include result.fusing.</p><p>Mesh &amp; material provides <strong>Copper melt · °C</strong> (1084.62), <strong>Latent heat · J/kg</strong> (206750), <strong>Pulse · s</strong> and <strong>Initial / ambient · °C</strong>. Initial temperature is independent of the temperature used for DC conductivity. The existing 150 °C limit screen remains separate. CLI: <code>--pulse 0.01 --ambient 25 --melting-temperature 1084.62 --latent-heat 206750 --output melt.json --html melt.html</code>.</p><p>The adiabatic balance integrates J²t = density × integral[Cp(T)/rho(T)] dT; the SI integral is multiplied by 1e-12 for J in A/mm². Cp is piecewise-linear <a href="https://janaf.nist.gov/tables/Cu-002.html">NIST-JANAF solid copper data, 250–1358 K</a>, converted using 0.063546 kg/mol. rho(T) = rho20[1 + alpha(T − 20 °C)] is an explicit high-temperature approximation. Eight-point Gaussian integration is used per Cp interval; resistivity ratios above four within an interval remain unsupported. Temperatures outside the Cp table leave the screen unknown without discarding DC results. Full melting adds density × latent heat / rho(Tm). The nominal latent input rounds <a href="https://janaf.nist.gov/tables/Cu-004.html">JANAF's solid/liquid enthalpy difference at 1358 K</a>: 13.138 kJ/mol / 0.063546 kg/mol = 206748 J/kg. See <a href="https://arxiv.org/abs/1503.01279">Guillet and Delamarre</a> for the temperature-dependent adiabatic energy-balance method; this implementation uses the stated interpolation and approximate linear resistivity.</p><p>Time is action / J². Pulse/action is not a physical damage fraction. Barrel melting I²t is action × actual solved axial metal area squared, including slots. An unambiguous straight-track match uses native width × local solved thickness as a nominal section; its local J is not integrated track current, and parallel plane copper changes current paths. Arc-only, plane-only and ambiguous cells retain unknown track section/I²t.</p><p>Up to twelve sheet regions and twelve barrels are ranked. Spatial suppression, per layer, separates sheet regions by twice max(0.05 mm, board XY extent / 64), so adjacent triangles do not crowd out remote candidates. This is local J-based screening, not geometric neck/minimum-cut detection. Nearby regions can merge; corner/contact singularities and mesh sensitivity require review. Proportional live-current changes scale times by 1/I² and pulse/action by I².</p><p><strong>The DC current distribution is frozen during heating. Melting is not fuse opening, clearing I²t, certified ampacity or protection coordination.</strong> Cooling, laminate heat transfer, expansion, current redistribution, liquid geometry, arcing and circuit interruption are omitted. Long predicted times are particularly affected by cooling. Infeasible requested loads remain diagnostics. Full 3D explicitly reports this screen unavailable; electrothermal/transient studies do not establish fault clearing. No copper is edited.</p></section><h2>Individual sink wheel control</h2><p>Ordinary scroll zooms. Ctrl+scroll over a sink pad changes only that load; grouped pads control their one assigned load. An orange ring identifies the sink. Slow scrolling adjusts finely; fast scrolling uses larger steps. Other copper and the Total control scale all loads proportionally, retaining the latest proportions.</p><p>Individual updates reuse the mesh and re-solve the fixed-temperature 2.5D electrical field in a background thread, including shared-copper currents, losses and melting screens. Rapid input is coalesced. Electrothermal, series/package, resistive-load and 3D cases require their own solve workflows.</p><h2>Cursor comparison</h2><p>Enable Cursor preview and choose Selected metric or All metrics. The readout appears beside the pointer, showing before/after current and signed field changes. Orange/blue distinguish increases/decreases, not pass/fail. Pending fields show computing markers. Whole-model loss is labelled separately; local samples in a projected all-layer view remain unknown until a layer is selected.</p><h2>Native inspector and cursor examples</h2><img src="help-current-preview.png" alt="Actual before and after current readout"><img src="help-inspector-tables-3.6.38.png" alt="Cross-selectable native parameter table"><img src="help-loss-tables-3.6.38.png" alt="Sortable native layer loss table"><p>Computed synthetic fixtures, with no private paths or edited numeric values. Drag column edges or scroll horizontally for full values; row tooltips expose full text.</p><p>AC studies are included in release 3.6.34.</p><p><img src="help-ac-study.png" alt="Native AC copper study: synthetic loop, RMS current density and harmonic tables" style="max-width:100%;height:auto"></p><h2>Easier ground and return setup</h2><p>For DC return voltage drop, open <b>Rails / ground returns…</b>, select the rail and choose <b>Set up ground / return…</b>. Review the ground net, supply-ground pads and every load-ground mapping together. Searchable pickers support multiple contacts. Footprint-based suggestions need explicit Apply; Advanced JSON remains available.</p><p><img src="help-return-ground.png" alt="Guided DC ground return mapping" style="max-width:100%;height:auto" width="650" height="489"></p><p>For a geometric reference-plane review, open <b>Return path</b>, choose its return net and click <b>Review return path</b>. <b>More return options</b> holds multiple nets, optional pads and sampling settings. Ground-name suggestions require confirmation. A sampled coverage result does not establish a solved current loop.</p><p><img src="help-return-setup.png" alt="Native return coverage review of a synthetic saved board" style="max-width:100%;height:auto" width="650" height="380"></p><h2>Current native examples</h2><h3>Mixed current/power endpoints</h3><img src="help-mixed-loads-3.6.38.png" alt="Computed mixed-load solve and grouped pin recommendations"><p>Synthetic 3.3 V copper fixture: grouped 1.65 W load plus 0.25 A current load; source 0.750252 A and copper loss 1.3862 mW. No converter dynamics are implied.</p><h3>Transient setup and results</h3><img src="help-transient-setup-3.6.38.png" alt="Engineering-unit transient setup"><img src="help-transient-results-3.6.38.png" alt="Computed explicit RLC load-step result"><h3>PDN capacitor bank</h3><img src="help-pdn-setup-3.6.38.png" alt="Explicit source and capacitor-bank inputs"><img src="help-pdn-results-3.6.38.png" alt="Sampled lumped impedance and target curves"><h3>AC setup and results · 3.6.40</h3><img src="help-ac-setup-3.6.40.png" alt="Quick AC loop inputs and live outgoing/return preview"><img src="help-ac-results-3.6.40.png" alt="AC heating summary cards and harmonic chart"><p>Open More → AC / SMPS copper study, enter the visible quick-loop dimensions and RMS ripple, then Run AC / ripple losses. Run uses the visible quick recipe directly. Custom tables support reviewed conductor/harmonic inputs; Inspect selects one large heating, impedance or cross-section chart. Transient/PDN parameters remain explicit lumped inputs. These are genuine native examples, not measured boards or platform-wide qualification. See <a href="USER_GUIDE.html#ac-and-switching-ripple-losses">the detailed AC workflow</a>.</p><h2>HTML and PDF reports</h2><p>Export HTML for interactive board views and exact probes. Use Print / save as PDF for browser printing. For a static PDF without a browser, run <code>python -m wayricad_runtime.tool_cli report-pdf review.html --output review.pdf --evidence review.json</code> after installing <code>wayricad[reports]</code>. The exporter retains text, tables and embedded PNG/JPEG figures. Canvas, SVG and unsupported views are explicitly listed as retained in HTML. Any tool JSON can use <code>python -m wayricad_runtime.tool_cli report result.json --html review.html --pdf review.pdf</code>; no analysis is recomputed.</p><h2>Differential voltage probes</h2><p>In Inspect → Probe, choose Set probe A and click solved sheet copper, then click B. Orange A and blue B markers show the locations. Read V(A) - V(B) in V/mV; Clear A/B returns to single-point inspection. In the all-layer projection select each physical layer explicitly.</p><img src="help-differential-probe.png" alt="Native two-point differential probe inspector on the analytical copper strip"><p>This is an analytical 10 × 1 mm, 35 µm copper strip at 1 V / 2 A, not a measured board. Barycentric evaluation uses the solved linear finite-element potential, not a display gradient or nearest-cell average. Empty space, drill holes and unknown nodes remain unknown. Both points must share one solved case reference. Full-volume and barrel-interior locations are unsupported. Cached point weights keep current updates fast.</p><p>Saved A/B points and their signed difference are included as a static report table. A browser click map is included up to 20,000 triangles; dense reports retain native/CLI probes without another large mesh payload. Use <code>python -m quick_pi_plugin.cli --probe-result result.json --probe-a 0 2 0.5 --probe-b 0 8 0.5 --output differential.json</code>. Layer IDs come from the saved mesh. This is DC probing, not an AC/transient waveform.</p><h2>Readable copper identifiers</h2><p>Via markers and results use V1, V2, and so on, in board-coordinate top-to-bottom then left-to-right order. All axial segments of one extracted physical via share its V number, with the layer span identifying each segment. Distinct saved objects are never merged because they share a location. Copper mesh cells use C1, C2, and so on, starting at one; these are not via or component references. IDs are scoped to the extracted model and cells may renumber when remeshed. The exported JSON retains original solver and PCB identities plus the display-identifiers mapping. Cross-selection still uses original identities.</p><h2>Blender visualization</h2><p>This feature is in the updated source; existing 3.6.40 installers do not contain it.</p><p>After a supported result, choose <b>Blender…</b>. Select a new export folder and optionally open an installed Blender. Export runs in a worker. Geometry and available result fields are preserved; animation uses stored computed samples. A static SI/DC result does not become a traveling-wave or transient simulation. Simplified component envelopes are not STEP solids. <a href="https://github.com/wayri/WayriCAD/blob/develop/wayricad_runtime/BLENDER.md">Full Blender workflow and limits</a>.</p></body></html>