[XPU] support HND layout

[zhenwei-intel]

Purpose

with PR #44455 and vllm-project/vllm-xpu-kernels#432

Now we can support HND layout in XPU, this unblocks PD disaggregation with heterogeneous TP.

Test Plan

VLLM_KV_CACHE_LAYOUT=HND ZE_AFFINITY_MASK=4 python examples/basic/offline_inference/generate.py --model Qwen/Qwen3-0.6B --enforce-eager

# PD disaggregation with heterogeneous TP
PREFILLER_TP_SIZE=2 DECODER_TP_SIZE=1 bash tests/v1/kv_connector/nixl_integration/run_xpu_disagg_accuracy_test.sh

Test Result

• acc (limit 100) and perf test (1k/1k) of qwen3-0.6B qwen3-30b-a3b

--- Performance Results ---
Model                          Layout      req/s  out_tok/s    ttft_ms    tpot_ms
--------------------------------------------------------------------------------
qwen3-0.6b                     HND          0.96     985.43     197.74      14.39
qwen3-0.6b                     NHD          0.96     983.80     192.10      14.41
qwen3-30b-a3b                  HND          0.19     193.33     600.87      73.26
qwen3-30b-a3b                  NHD          0.20     199.79     598.49      70.91

--- Accuracy Results ---
Model                          Layout   Task       Filter             Metric          Value   Stderr
----------------------------------------------------------------------------------------------------
qwen3-0.6b                     HND      gsm8k      strict-match       exact_match      0.44   0.0499
qwen3-0.6b                     NHD      gsm8k      strict-match       exact_match      0.44   0.0499
qwen3-30b-a3b                  HND      gsm8k      strict-match       exact_match      0.98   0.0141
qwen3-30b-a3b                  NHD      gsm8k      strict-match       exact_match      0.98   0.0141

---

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• The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)".
• The test plan, such as providing test command.
• The test results, such as pasting the results comparison before and after, or e2e results
• (Optional) The necessary documentation update, such as updating supported_models.md and examples for a new model.

[claude]

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[zhenwei-intel]

cc @zufangzhu @jikunshang @yma11 PTAL.