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[Add] add sycl implementation for dequantize_and_gather_k_cache#447

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[Add] add sycl implementation for dequantize_and_gather_k_cache#447
wangshier108 wants to merge 1 commit into
vllm-project:mainfrom
wangshier108:hanying/gather_k_cache

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Purpose

Adds SYCL implementation of xpu_v4_gather_k_cache_bf16 used by DeepseekV4 SWA prefill on Intel XPU.

Test Plan

Testing

pytest -q tests/test_cache.py::test_dequantize_and_gather_k_cache

Benchmark

   python benchmark/bench_xpu_dequantize_and_gather_k_kernel.py --backend both 

Test Result

SWA-only (compress_ratio=1, block_size=64)

seq_lens Triton (kernel µs) SYCL (kernel µs) kernel_Speedup Triton (e2e µs) SYCL (e2e µs) e2e_Speedup Triton BW% SYCL BW%
128 4.50 3.50 1.28x 33.90 11.70 2.89x 10.00% 12.80%
512 12.40 3.90 3.22x 34.40 11.60 2.96x 14.56% 46.80%
1024 22.80 4.90 4.64x 33.80 11.30 2.98x 15.86% 73.50%
8192 157.30 35.10 4.48x 202.50 42.70 4.74x 18.40% 82.40%
16384 345.50 65.30 5.29x 405.30 75.00 5.40x 16.75% 88.70%
32768 716.10 139.90 5.12x 758.30 156.00 4.86x 16.16% 82.70%
65536 1428.50 270.30 5.29x 1453.90 272.10 5.34x 16.21% 85.70%
102400 2230.70 420.30 5.31x 2235.20 467.40 4.78x 16.23% 86.10%

C4 compressed full gather (compress_ratio=4, block_size=64)

logical_seq api_seq Triton (µs) SYCL (µs) kernel_Speedup Triton (e2e µs) SYCL (e2e µs) e2e_Speedup Triton BW% SYCL BW%
128 32 3.10 3.50 0.87x 33.30 11.40 2.93x 3.68% 3.20%
2048 512 12.20 4.30 2.85x 33.10 11.40 2.90x 14.85% 42.30%
4096 1024 22.70 5.10 4.45x 32.80 11.30 2.90x 15.96% 71.00%
8192 2048 42.50 10.30 4.13x 51.40 13.00 3.95x 17.02% 70.20%
16384 4096 81.50 18.50 4.40x 102.30 22.10 4.62x 17.74% 78.00%
32768 8192 156.20 31.90 4.90x 197.40 36.40 5.42x 18.53% 90.90%
65536 16384 344.00 65.00 5.29x 407.60 73.50 5.55x 16.82% 89.00%
102400 25600 553.70 108.70 5.09x 599.10 121.60 4.93x 16.34% 83.20%

C128 compressed full gather (compress_ratio=128, block_size=2)

logical_seq api_seq Triton (µs) SYCL (µs) kernel_Speedup Triton (e2e µs) SYCL (e2e µs) e2e_Speedup Triton BW% SYCL BW%
8192 64 2.90 3.50 0.84x 32.50 11.40 2.86x 7.68% 6.40%
16384 128 3.70 3.90 0.95x 32.70 11.50 2.84x 12.32% 11.70%
32768 256 6.50 4.00 1.61x 33.20 11.60 2.87x 13.90% 22.40%
65536 512 11.70 3.80 3.07x 32.50 11.30 2.88x 15.42% 47.40%
102400 800 19.30 4.70 4.06x 32.20 11.40 2.84x 14.67% 59.50%

Copilot AI review requested due to automatic review settings July 3, 2026 02:12

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Pull request overview

Adds a new XPU (SYCL) implementation of dequantize_and_gather_k_cache to support DeepseekV4 SWA prefill, including op registration plus a correctness test and a benchmarking script for Triton vs SYCL comparisons.

Changes:

  • Implemented and registered the SYCL kernel and dispatcher entry for dequantize_and_gather_k_cache under _C_cache_ops.
  • Added a reference implementation + pytest to validate correctness across block sizes and optional gather_lens.
  • Added a benchmark script to compare Triton and SYCL performance for representative DeepseekV4 scenarios.

Reviewed changes

Copilot reviewed 6 out of 7 changed files in this pull request and generated 7 comments.

Show a summary per file
File Description
csrc/cache.cpp Adds the SYCL kernel implementation and host-side argument validation/dispatch.
csrc/ops.h Declares the new cache op C++ signature.
csrc/torch_bindings.cpp Registers the new op schema and XPU implementation in PyTorch dispatcher.
tests/register_ops.py Exposes a Python wrapper for calling the new _C_cache_ops op.
tests/test_cache.py Adds a CPU reference + pytest for dequantize_and_gather_k_cache.
benchmark/bench_xpu_dequantize_and_gather_k_kernel.py New benchmark comparing Triton vs SYCL, with optional SYCL validation.
bench_xpu_dequantize_and_gather_k_kernel.py Present as an empty file in the PR context (purpose unclear).

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Comment thread csrc/cache.cpp
Comment on lines +1309 to +1314
TORCH_CHECK(offset >= 0, "offset must be >= 0");
TORCH_CHECK(offset <= out.size(1), "offset exceeds out token dimension");

const int64_t min_block_bytes =
block_size * vllm::kDeepseekV4TokenDataBytes +
block_size * vllm::kDeepseekV4ScaleDim;
Comment on lines +1 to +3
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
"""Benchmark DeepseekV4 dequantize_and_gather_k_cache on XPU.
Comment on lines +23 to +25
REPO_ROOT = Path(__file__).resolve().parents[2]
if str(REPO_ROOT) not in sys.path:
sys.path.insert(0, str(REPO_ROOT))
Comment on lines +45 to +52
sycl_root_arg = _peek_cli_value(argv, "--sycl-kernels-root")
candidate_root = (
REPO_ROOT.parent / "applications.ai.gpu.vllm-xpu-kernels"
if sycl_root_arg is None
else Path(sycl_root_arg).resolve()
)
if candidate_root.exists() and str(candidate_root) not in sys.path:
sys.path.insert(0, str(candidate_root))
Comment on lines +150 to +152
def _default_sycl_kernels_root() -> Path | None:
p = REPO_ROOT.parent / "applications.ai.gpu.vllm-xpu-kernels"
return p if p.exists() else None
Comment on lines +66 to +69
from vllm.v1.attention.ops.deepseek_v4_ops.cache_utils import (
_dequantize_and_gather_k_kernel,
dequantize_and_gather_k_cache,
)
Comment on lines +83 to +86
KERNEL_NAME_SUBSTRING = "dequantize_and_gather"
B60_PEAK_BANDWIDTH_GBPS = 456.0
B60_CACHE_SIZE_MB = 512

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2 participants