ES0392 errata coverage review + AXI-SRAM (§2.2.10) presence guard - #65
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Cross-referenced the STM32H750 errata (ES0392 Rev 15) against the firmware and Renode models. Findings: - The three errata that touch our hot paths are already handled and verified in code: §2.2.10 (AXI SRAM read corruption — AXI_TARG7_FN_MOD poke, gated to pre-rev-V), §2.7.4 (QUADSPI internal timing dance), §2.2.21 (480 MHz gated to rev V), plus §2.6.6/.7 SDRAM timing side-stepped in sdram.rs. - §2.1.1 (write-through D-cache corruption) audited clean: the only write-through MPU region is read-only QSPI XIP; every writable region is non-cacheable or write-back. - Ruled out §2.7.6, §2.9.x, §2.5.x, §2.2.17/.24, §2.2.3, §2.19.x for our usage. - Noted latent traps (§2.1.5 DMB-after-invalidate for the DMA cache test, §2.7.5 last-FSIZE-byte read) — no action yet. New `docs/errata-coverage.md` records the full table; cross-linked from renode-fidelity.md. §2.2.10 is the same silent-omission class as the SDNWE=PH5 pin bug and the FMC BCR1.FMCEN gate — un-modellable, so guard it with a presence assertion: `renode/errata_workarounds.robot` boots the real bootloader and checks AXI_TARG7_FN_MOD is written on pre-rev-V / rev-Y silicon and left untouched on rev V. Backed by a small AXI-interconnect ArrayMemory (0x5100_8000) in daisy_seed.repl so the poke lands observably. 3/3 green; clocks_boot unaffected. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This was referenced Aug 16, 2026
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Summary
A deliberate cross-reference of the STM32H750 device errata (ES0392 Rev 15) against this firmware and its Renode models, prompted by a "revisiting the RM and errata, anything we're missing?" review. Honest conclusion: nothing load-bearing is missing — the errata that touch our hot paths are already handled. This PR captures that review durably and adds one regression guard for the highest-value un-modellable workaround.
What's here
docs/errata-coverage.md— the full coverage table, in three buckets:AXI_TARG7_FN_MODpoke, gated to pre-rev-V, mirrors libDaisy), §2.7.4 (QUADSPI internal-timing dance), §2.2.21 (480 MHz gated to rev V), §2.6.6/.7 (SDRAM timing side-stepped insdram.rs).renode/errata_workarounds.robot— §2.2.10 is the same silent-omission class as the SDNWE=PH5 pin bug and the FMCBCR1.FMCENgate: a required register poke Renode can't model behaviourally. Guard it with a presence assertion (à laqspi_ncs_pinmux.robot): boot the real bootloader and assertAXI_TARG7_FN_MODis written on pre-rev-V / rev-Y silicon and left untouched on rev V. A small AXI-interconnectArrayMemory(0x5100_8000) indaisy_seed.replmakes the poke land observably.Verification
renode/errata_workarounds.robot— 3/3 green (two-sided: pre-V/rev-Y must write1, rev-V must leave0, proving the write is conditional).renode/clocks_boot.robot— still 3/3 green (the shared-platform neighbour; the added memory is additive).No firmware behaviour changes — docs + one Renode model memory + one new test.
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