test(renode): FMC model — AHB3 bus-clock gate + fix a #55 test regression

[twitzelbos]

Summary

Extends the FMC SDRAM model's precondition checks and repairs a latent test breakage that #55's FMCEN work introduced.

Model (STM32H7_FMC_SDRAM.cs)

• Adds the RCC_AHB3ENR.FMCEN (bit 12) bus-clock gate check — a separate enable from the BCR1.FMCEN controller enable already modelled. If the FMC's AHB3 clock is gated, the SDCMR init commands make no progress and the window stays unusable. Opt-in via a settable RccAhb3enrAddress (default 0 = off), mirroring the QuadSPI model's NcsGpioModerAddress, so register-poke tests that don't model RCC are unaffected. The model takes an injected IMachine to read RCC over the sysbus (the QuadSPI pattern; registration unchanged).

Tests (sdram_fmc.robot)

• Fixes a regression from fix(sdram): cold-init bring-up — FMC controller enable + PH5/SDNWE pin #55: Run FMC Init Sequence never set BCR1.FMCEN, so once fix(sdram): cold-init bring-up — FMC controller enable + PH5/SDNWE pin #55 added the controller-enable gate, every "…After Init" round-trip test was gated off and failing — masked because the Renode suite isn't in blocking CI. Now the init sequence enables the controller.
• Gives the ordering ("Skipping X Leaves SDRAM Gated") tests the controller too, so they're gated by the missing JEDEC step (what they claim to test) rather than trivially by a missing FMCEN.
• Adds a dedicated BCR1.FMCEN-gate test (that gate had none) and the AHB3 bus-clock gate pair (off → gated; on → usable, so the check isn't always-fail).

Test

renode/sdram_fmc.robot — 21/21 pass (was failing 5 "After Init" tests on main before this).

Note

sdram_init.robot (real firmware, stock RCC) is left as-is — the AHB3 check is validated here with the stub RCC (sticky RW) where the gate bit is fully controlled. Wiring it into the real-firmware path is a possible follow-up.

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