Minimal bare-metal PS UART echo on Versal AI Edge VD100 — no Linux, no Yocto, instant debug output for HW engineers
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Apr 19, 2026 - C++
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xcve2302
Here are 16 public repositories matching this topic...
Post-link Vitis pipeline platform for VD100 (XCVE2302). Add new HLS or AIE kernels to the existing Vitis region without starting a new Vivado project. Built from vd100_ma_system_project post-link XSA.
platform embedded fpga amd xilinx vivado noc versal axi hardware-platform kernel-integration xcve2302 vd100 aie-ml
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Apr 11, 2026 - C
Vivado 2025.2 block design for VD100 (XCVE2302) — CIPS, NoC, AIE-ML, AXI interrupt controller, MyLEDIP. Reusable hardware platform for Vitis AIE kernel projects. Exports XSA for vd100_platform. No VCK190 required.
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Apr 11, 2026 - VHDL
Vitis 2025.2 system project for VD100 (XCVE2302) — v++ link + package for AIE-ML v2 + HLS kernel integration. Produces aie.xclbin and BOOT.BIN CDO artifacts. Reusable: swap AIE kernel or add HLS kernels without new project.
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Apr 18, 2026 - CMake
First documented end-to-end PL + AIE-ML + PS pipeline on Versal AI Edge XCVE2302 (VD100). MA crossover trading signal via HLS DMA + AIE graph + XRT host app. No VCK190. No MATLAB. Ethereum audit log on Hardhat.
fpga hls amd xilinx yocto embedded-linux versal trading-systems moving-average xrt vitis xcve2302 aie-ml
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May 24, 2026 - C++
Yocto Scarthgap meta layer for VD100 (XCVE2302) — XRT 2025.2, zocl, AIE-ML pipeline. Fixes undocumented BOOT.BIN CDO gap that leaves all AIE tiles clock-gated under Linux. Submodule of versal-ai-edge-vd100-linux.
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Apr 14, 2026 - Batchfile
Custom Yocto layer for the Alinx VD100 (Versal AI Edge Series XCVE2302-SFVA784-1LP-E-S). Adds AXI-lite PL LED kernel driver (myledip) via M_AXI_FPD — PS LED via libgpiod, PL LED via /dev/plledip. Custom AXI-lite IP (MyLEDIP), Linux platform driver, C++ demo. AMD EDF 25.11 / Scarthgap.
build kernel-module linux-kernel device-tree yocto embedded-linux versal platform-driver cortex-a72 axi-lite ai-edges xcve2302 amd-fpga m-axi-fpd ps-pl-codesign
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Apr 4, 2026 - VHDL
Custom Yocto Linux bring-up on Alinx VD100 (XCVE2302). v1: SD/Ethernet/USB. v2: I2C/GPIO/PL LED/kernel driver. v3: XRT + AIE-ML pipeline + Ethereum. No VCK190. No MATLAB. AMD EDF 25.11 / Scarthgap.
fpga ethereum device-tree ethereum-contract vivado yocto embedded-linux uboot versal xrt libgpiod cortex-a72 amd-xilinx xcve2302 vd100 system-device-tree aie-ml zocl
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Apr 14, 2026
Live Binance WebSocket feed → MA crossover signal → Ethereum smart contract on Versal AI Edge XCVE2302 (VD100). SW mode: 1440ns on A72. AIE-ML v2 XRT pipeline integrated and benchmarked. XRT architectural findings documented.
fpga websocket ethereum solidity xilinx yocto embedded-linux versal moving-average binance xrt trading-signals xcve2302 vd100 aie-ml
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Aug 13, 2026 - C++
Custom Yocto layer for the Alinx VD100 (XCVE2302-SFVA784-1LP-E-S). SD boot, Ethernet, USB, SSH, I2C, LM75, EEPROM, sysmon, and PS LED via libgpiod. AMD EDF 25.11 / Scarthgap. No VCK190 — accessible Versal bring-up on a $1,285 board.
fpga linux-kernel device-tree xilinx yocto embedded-linux edf versal meta-layer cortex-a72 scarthgap xcve2302 vd100 amd-fpga
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Apr 2, 2026 - SystemVerilog
AIE-ML moving average crossover kernel for VD100 (XCVE2302). Dual MA (fast 10 / slow 50 period), BUY/SELL/HOLD signal. 56 int32 samples/iteration via HLS DMA. Used in vd100-aie-pipeline. Vitis 2025.2.
fpga hls amd signal-processing xilinx versal trading-systems moving-average xrt vitis xcve2302 vd100 aie-ml
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Apr 14, 2026 - C++
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