verible

Here are 13 public repositories matching this topic...

chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server systemverilog-parser systemverilog-developer sv-lrm verible

Updated Sep 23, 2026
C++

a2k-hanlon / linter-veriloghdl

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Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

compiler linter slang verilog systemverilog hdl iverilog icarus verilator verible

Updated Jul 12, 2023
CoffeeScript

PyFPGA / containers

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Containers for FOSS tools

slang ghdl yosys ghdl-yosys-plugin verible surelog synlig vhd2vl sv2v yosys-slang

Updated Sep 7, 2026
Shell

rothej / optical-flow-fpga

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Real-time Lucas-Kanade optical flow implemented on FPGA (Nexys A7-100T) for computer vision applications. Uses Python for algorithm verification and benchmarking.

computer-vision fpga xilinx vivado optical-flow systemverilog lucas-kanade verilator cocotb verible

Updated Jul 2, 2026
SystemVerilog

stornado / Open-IC-DEV

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Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh，vscode 等开源工具链的开发环境。

docker debian vscode systemverilog systemc uvm system-verilog iverilog verilator verible

Updated Jan 7, 2024
Dockerfile

capopaul / Public-Verilog-Design-Flow-And-Environment

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Provide a basic structure to starts a Verilog or Systemverilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)