systemverilog-test-benches

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dragprog / neoh

NeoH (or NeoHDL) is a declarative HDL, proficient in creating extremely fast and secure testbenches, with complete support for SystemVerilog, as it transpiles into said HDL.

rust transpiler systemverilog hdl testbenches hardware-verification systemverilog-test-benches

Updated Jul 13, 2026
Python

VRM21-Studios / VRM21-CPU-RISC-V-Series

Star

Parameterized RISC-V CPU series by VRM21-Studios, featuring a synthesizable RV32I core, interrupt architecture, timer, SoC wrapper, GCC firmware, and verification testbenches.

gcc rtl verilog vivado systemverilog gcc-compiler verilog-hdl risc-v rv32i systemverilog-simulation verilog-project vivado-simulator rv32i-processor verilog-2001 systemverilog-test-benches gcc-build

Updated Sep 8, 2026
Verilog

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