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Jun 6, 2020 - C
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single-port
Here are 8 public repositories matching this topic...
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
fpga ram hardware verilog synchronous testbench digital-circuits hardware-description-language single-port fpga-programming memory-design
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Aug 24, 2024 - Verilog
Deploy nodejs/react app on a single port/domain.. Git repo for the corresponding medium story.
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Feb 23, 2021 - HTML
static-files-server written in typescript usable as a command-line-tool (or runtime library)
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May 6, 2025 - TypeScript
基于 Rust 的 S3 兼容对象存储服务，内置单端口管理控制台，支持集群管理、复制与纠删码。
rust replication raft iam self-hosted distributed-storage erasure-coding object-storage web-console single-port s3-compatible
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Jul 2, 2026 - Rust
AI-powered note app: URL/text/file → AI analysis → 8-tab structured output. React 19 + Express 5, ~6k lines. 8 backend modules incl. TF-IDF vector store with zero-key degradation and model failover.
react express typescript knowledge-graph failover tf-idf fullstack drawio single-port rag ai-notes openai-compatible
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Sep 17, 2026 - TypeScript
This repository contains the verilog codes for writing memories, especially RAM (single, dual, 3 port) using multiple methods in VIVADO DESIGN SUITE 2020.2
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May 4, 2025 - Verilog
Run multiple react application on a single port using nginx
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Dec 11, 2022 - TypeScript
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