1-bit full adder + 4-bit ripple-carry adder in VHDL — verified on Basys 3 hardware, in Vivado simulation, and exhaustively in CI with self-checking GHDL testbenches
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Updated
Jul 24, 2026 - VHDL
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self-checking-testbench
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Phase-2 Cycle-3: Verification Fundamentals
randomization assertions constrained-random-verification functional-coverage class-based-verification cross-coverage self-checking-testbench
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Updated
Aug 30, 2026 - SystemVerilog
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