OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
A VHDL (and eventually Memristive) implementation of ESA's SNN4Space project
Sample code to demonstrate how to use GNA unit in Intel CPUs for inferencing.
High-efficiency, resource-optimized Neural Network Computation Engine in SystemVerilog. Leverages bit-serial arithmetic to minimize hardware footprint (LUTs/Registers) without compromising precision. 🏆 Gold Winner @ VLSI Hackathon, NIT Jamshedpur.
Verilog accelerator for FC1-Norm-ReLU-FC2 inference using a 4x4 weight-stationary systolic array
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