moore-fsm

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abhichandra586 / 04-finite-state-machines

Finite State Machines in Verilog — Moore FSM, Mealy FSM, Traffic Light Controller, Sequence Detector (1011), UART Transmitter, UART Receiver, SPI Master, Debounce Circuit | Step 4 of 8 toward a 16-bit pipelined RISC processor

fsm fpga verilog spi debounce uart icarus-verilog gtkwave vlsi digital-design traffic-light sequence-detector rtl-design mealy-fsm moore-fsm

Updated Jun 29, 2026
Verilog

NDeekshitha25 / Sequence-Detector-FSM

Star

SystemVerilog implementation of Moore and Mealy FSM-based 1111 sequence detectors with overlapping and non-overlapping detection, verified using Cocotb.

fsm rtl verilog systemverilog digital-design cocotb sequence-detector hardware-design mealy-fsm moore-fsm

Updated Jul 2, 2026
SystemVerilog

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