Stoic-V: a deterministic RV32IM + Zba/Zbb/Zbs + Zicsr (M-mode) RISC-V soft core in SystemVerilog. No caches, speculation, or branch prediction, so timing is operand-independent and WCET is statically analysable. Drop-in replacement for the AMD MicroBlaze-V via the LMB v10 interface; closes 250 MHz on UltraScale+.
real-time fpga riscv systemverilog lmb wcet deterministic hdl risc-v soft-core rv32 ultrascale hard-real-time cpu-core microblaze-v
-
Updated
Jun 13, 2026 - SystemVerilog