Mini-project for the grading of Digital system design with FPGA course - IISc | year 2024. RISC V 8 bit 5 stage pipelined processor verilog code.
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Apr 17, 2024 - Verilog
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SHIELD-AI: a Kubernetes operator combining online ML (River HTR + Half-Space-Trees) with a TLA+-verified safety shield. 273,702 model-checked states, 0 violations, 53/53 unit tests, every paper claim traceable to evidence-freeze.md (56 sourced, 0 unsourced). MIT licensed. M.Tech project, 2026.
kubernetes kafka prometheus autoscaling formal-verification self-healing tla-plus online-machine-learning m-tech mtech-project river-ml safety-shield
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Sep 11, 2026 - Python
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