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ip-xact

Here are 14 public repositories matching this topic...

kactus2 / kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

design fpga hardware eda ip-xact reuse hdl mpsoc system-on-chip

Updated Jun 9, 2026
C++

olofk / ipyxact

Python-based IP-XACT parser and utilities

ip-xact

Updated Jun 13, 2024
Python

oddball / ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

vhdl verilog ip-xact systemverilog

Updated Jan 28, 2026
Python

SystemRDL / PeakRDL-ipxact

Import and export IP-XACT XML register models

asic fpga eda ip-xact register-descriptions systemrdl-compiler ipxact

Updated Nov 5, 2025
Python

edaa-org / pyEDAA.IPXACT

An IP-XACT DOM for IEEE 1685-2014 in Python.

python parser xml ip-xact fileformat accellera edaa

Updated Feb 23, 2026
Python

kactus2 / ipxactexamplelib

Contains examples to start with Kactus2.

example-data ip-xact

Updated Aug 5, 2024
Verilog

edaa-org / IPXACT-Schema

This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.

xml xml-schema ip-xact

Updated May 12, 2025
HTML

kactus2 / pulpinoexperiment

IP-XACT packaging of Pulpino by pulp-platform.org: https://github.com/pulp-platform/pulpino

ip-xact example-project risc-v pulpino

Updated Dec 11, 2019
Verilog

iDoka / ipxact-cli-tools

IP-XACT based CLI-tools

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

Updated Apr 12, 2017
Mako

iDoka / ipyxact

Python-based IP-XACT parser

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

Updated Mar 27, 2017
Python

Luke7412 / IpLibrary

Library containing various VHDL IPs

rtl ip xilinx vivado ip-xact systemverilog ipxact arty-a7 packaged-ip

Updated Jan 5, 2024
SystemVerilog

kactus2 / k2xml_converter

A conversion tool for different IP-XACT versions.

converter xslt ip-xact

Updated Nov 27, 2019
XSLT

episource / vivado-training

Various custom training projects related to Xilinx Zynq development.

c fpga zynq vhdl xilinx vivado ip-xact zybo xilinx-sdk

Updated Nov 4, 2017
HTML

anovickis / graphify-rtl

RTL/hardware fork of graphify. Upstream's SystemVerilog extractor produced no edges; this fixes it (modules, instances, packages, includes, interfaces, binds) and adds Make, Tcl, IP-XACT, SymbiYosys and Verilator-testbench extractors — turning an HDL IP catalog into a queryable knowledge graph.

hardware eda rtl knowledge-graph verilog ip-xact systemverilog formal-verification

Updated Jun 9, 2026
Python

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