Digital Design Equivalence Checking
Logic circuit analysis and optimization
A Web-based tool that helps analyze the correctness and equivalence of programs using formal methods.
Bounded equivalence checker that proves an AI-refactored function matches the original—or finds a counterexample—using differential testing and Z3 symbolic execution
Context-verified, error-budget-aware decomposition selection for Toffoli networks. Companion code to arXiv:2606.31791 (Bartkiewicz & Tulewicz, submitted to Quantum).
Combinational logic equivalence check: two gate-level netlists in, an equivalence verdict (with counter-example) out.
Lean formalization of how behavioral equivalence checking can be generalized through abstract intrepretation
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