中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
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Mar 21, 2021 - Verilog
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cpu-designs
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Codex skills for Chisel/RISC-V processor development: microarchitecture, RTL verification, Vivado timing analysis, and FPGA optimization.
fpga chisel rtl chisel3 vivado risc-v processor-design cpu-designs loongarch agent-skills codex-cli codex-skills
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Sep 6, 2026 - Python
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