A bunch of MIPS (assembly) programming exercises and problems done in college as a part of the course Computer Architecture (CS F342).

Compilation of my Computer Architrcture and Verilog Courses at UW. Documentation for the code included in the individual directories.

[ECE NTUA] Computer Architecture class 2016 - 2017

32-bit 5-stage pipelined RISC-V CPU (RV32I) in Verilog HDL. Supports ADD, SUB, AND, OR, LW, SW, BEQ, BNE with hazard handling (forwarding, stalls, flushes). Verified using testbenches and GTKWave, achieving CPI ≈ 1.0 on hazard-free execution.

Lab assignments and some practise done for the Computer Architecture course at BITS Pilani

Nand2Tetris - Building a simulated Computer System from First Principle

ENGR3410 PDFs

Custom malloc/free implementation in C using a 4-bin segregated free list with address-sorted bins, first-fit placement, block splitting, and deferred coalescing. Includes a heap consistency checker verifying alignment, ordering, overlap, and free-status invariants