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A lightweight, simulator-agnostic SystemVerilog testbench framework for structured testing without UVM.

Apache-2.0 license

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LICENSE		LICENSE
README.md		README.md

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svtbx

A lightweight, simulator-agnostic SystemVerilog testbench framework for structured testing without UVM.

About

A lightweight, simulator-agnostic SystemVerilog testbench framework for structured testing without UVM.

Apache-2.0 license

0 stars

0 watching

Report repository

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