Hi there! 👋 I'm Thejas K G

🔬 Senior Design Verification Engineer | RTL Design | SystemVerilog Enthusiast | coco-tb Enthusiast | Formal Enthusiast| Low power Enthusiast .

Passionate about ensuring silicon works right the first time through comprehensive verification methodologies and innovative testbench architectures and develop the front-end research in Design Verification Engineer.

🚀 What I Do

• Verification Methodologies: UVM, OVM, Constrained Random Verification
• Languages: SystemVerilog, Verilog, VHDL, C/C++, Python
• Tools: Cadence (Xcelium, JasperGold), Synopsys (VCS, Verdi), Mentor (QuestaSim)
• Protocols: AXI, AHB, APB, PCIe, USB, I2C, SPI, UART
• Specialties: CPU/GPU verification, Memory subsystems, Interface protocols

💼 Current Focus

• 🎯 Advanced UVM testbench development
• 🔍 Formal verification and property checking
• 🧠 AI-assisted verification flows
• 📊 Coverage-driven verification strategies

📫 Let's Connect

• LinkedIn: www.linkedin.com/in/thejas-koneripalli-govindarajulu-1a2980b3
• Email: [thejaskg@yahoo.com]