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8 followers · 13 following
  • Dresden, Germany
  • 08:29 (UTC +02:00)

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thatdanish/README.md

Hi there !👋

I am a master's student at Technische Universität Dresden (TUD) with specialization in Nanoelectronic Systems. I have my keen intrestes in ASIC design, FPGA programming, machine learning (ML) and other similar domains. If we share our fonds, I will be happy to connect 😃.

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  1. RippleV RippleV Public

    A pipelined RISC-V CPU core implementation with control & data hazard handling, fully open source.

    SystemVerilog

  2. I2C-Interface I2C-Interface Public

    RTL implementation of single controller I2C protocol.

    Python

  3. SPI SPI Public

    RTL implementation of Serial Peripheral Interface (SPI)

    SystemVerilog

  4. 8bit-UART 8bit-UART Public

    RTL implementation of Universal Asynchronous Receiver-Transmitter (UART) protocol.

    SystemVerilog

  5. AbstractDesigns AbstractDesigns Public

    Collection of abstract RTL codes (design) built on Icarus.

    SystemVerilog

  6. Priority_Traffic_Surveillance Priority_Traffic_Surveillance Public

    This open sourced project is aimed at solving a major problem caused due to continuously increasing traffic on the roads, during rush hours.

    Jupyter Notebook 1