Bypass final RET routing write

[guosran]

Summary

Addresses #292 with a minimized final-RET register bypass fix. This PR only updates RegisterClusterRTL.py and its focused test.

Changes

• Bypass a same-cycle routing write to the FU path only for the final RET case.
• Preserve existing register-bank priority for other cases.
• Add a concrete example as an inline test comment.

No new ports or interfaces are introduced.

[guosran]

Concrete example: the final RET control writes routing token 42 into register 3 and reads register 3 for the FU in the same cycle. The register file read sees the old value in that cycle, so this PR bypasses only this exact final-RET routing-write case.

[guosran]

Concrete example:
RET may need the value written by routing crossbar in the same final control step.

same cycle:
routing_xbar writes r3 = 99
RET reads r3

Before:
RET could read the old r3 value from the register bank.

After:
RegisterClusterRTL bypasses the routing write data to the FU/RET path for this final RET case.