A complete SystemVerilog verification environment for an AXI4-Lite Slave featuring constrained-random stimulus generation, mailbox-based communication, self-checking scoreboard, protocol verification using SystemVerilog Assertions (SVA), and waveform analysis.
This project verifies the functionality and protocol compliance of an AXI4-Lite Slave using a custom SystemVerilog testbench.
The verification environment includes:
- Constrained-random transaction generation
- Mailbox-based communication
- Driver, Monitor, Generator, Environment
- Self-checking Scoreboard
- SystemVerilog Assertions (SVA)
- Functional verification
- Protocol compliance checking
- Waveform analysis
AXI4-Lite-Verification/
│
├── rtl/
│ ├── axi_lite_slave.sv
│ └── axi_if.sv
│
├── verification/
│ ├── transaction.sv
│ ├── generator.sv
│ ├── driver.sv
│ ├── monitor.sv
│ ├── scoreboard.sv
│ ├── environment.sv
│ ├── axi_assertions.sv
│ └── testbench.sv
│
├── axi_waveform.jpg
│
└── README.md
The custom verification environment consists of the following components:
- Generates constrained-random read and write transactions.
- Sends transactions to the driver using a mailbox.
- Drives AXI4-Lite interface signals.
- Performs write and read handshakes.
- Communicates with the DUT.
- Observes DUT interface activity.
- Captures completed transactions.
- Sends transaction information to the scoreboard.
- Stores expected memory contents.
- Compares DUT output with expected data.
- Reports PASS/FAIL results automatically.
- Connects all verification components.
- Controls overall simulation flow.
The following protocol assertions are implemented:
- Reset verification
- Write address handshake
- Write data handshake
- Write response timing
- BRESP validity
- Read address handshake
- Read response timing
- RRESP validity
- RVALID hold until handshake
- BVALID hold until handshake
- Stable AWADDR during wait state
- Stable WDATA during wait state
- Stable ARADDR during wait state
- Valid write address range
- Valid read address range
- AWVALID
- AWREADY
- AWADDR
- WVALID
- WREADY
- WDATA
- BVALID
- BREADY
- BRESP
- ARVALID
- ARREADY
- ARADDR
- RVALID
- RREADY
- RDATA
- RRESP
Generator
│
▼
Driver
│
▼
AXI4-Lite Slave DUT
│
▼
Monitor
│
▼
Scoreboard
The waveform below demonstrates a complete AXI4-Lite transaction flow, including reset, write transaction, read transaction, protocol handshakes, response generation, and internal DUT state transitions.
The waveform illustrates:
- Reset sequence
- Write address handshake (AWVALID/AWREADY)
- Write data handshake (WVALID/WREADY)
- Write response (BVALID/BREADY)
- Read address handshake (ARVALID/ARREADY)
- Read data response (RVALID/RREADY)
- FSM state transitions
- Internal write address register updates
- Transaction counter activity
[DRV] RESET DONE
[GEN] Generated Write Transaction
[DRV] Driving Write Address
[MON] Captured Write Transaction
[SCO] DATA STORED
[GEN] Generated Read Transaction
[DRV] Driving Read Address
[MON] Captured Read Transaction
[SCO] DATA MATCHED
- Custom SystemVerilog Verification Environment
- Mailbox-Based Communication
- Constrained-Random Verification
- Self-Checking Scoreboard
- SystemVerilog Assertions (SVA)
- AXI4-Lite Protocol Verification
- Functional Verification
- Waveform Analysis
- Modular Testbench Architecture
- SystemVerilog
- QuestaSim / ModelSim
- EPWave
- Git
- GitHub
- Functional Coverage
- Coverage-Driven Verification
- UVM-Based Testbench
- Automated Regression Testing
- Error Injection Testcases
- AXI4 Full Burst Transaction Support
Shreya Sharma
Electronics & Communication Engineering
Skills: RTL Design • SystemVerilog • Design Verification • AXI4-Lite • SystemVerilog Assertions (SVA) • Digital Design • FPGA • VLSI
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