Verilog Designs

A collection of Verilog HDL codes for practicing and understanding digital design concepts.
It includes both combinational and sequential circuits, implemented along with their testbenches.

The goal of this repo is to build a strong foundation in RTL design, digital electronics, and VLSI basics.

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📂 Table of Contents

🔸 Combinational Circuits

• 4:1 MUX | Testbench
• 4:2 Priority Encoder | Testbench
• 3:8 Decoder | Testbench
• 4-bit Comparator | Testbench
• Half Adder | Testbench
• Full Adder | Testbench

🔸 Sequential Circuits

• D Flip-Flop (Sync) | Testbench
• JK Flip-Flop | Testbench
• D Latch Async | Testbench
• Up Counter | Testbench
• Up/Down Counter | Testbench
• Mod Counter | Testbench
• Range Up Counter | Testbench
• Frequency Divider by 2 | Testbench
• Frequency Divider by 4 | Testbench

🔸 Shift Registers

• Left Shift Register | Testbench
• Right Shift Register | Testbench
• Universal Shift Register | Testbench

🔸 Memory & Other Designs

• ALU 4-bit | Testbench
• 8-bit Twin Register | Testbench
• Single Clock FIFO | Testbench
• Dual Clock FIFO | Testbench
• Single Port RAM | Testbench
• Dual Port RAM | Testbench

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🖥️ How to Run

You can simulate the designs using Icarus Verilog or ModelSim.

Example (using Icarus Verilog + GTKWave):

# Compile design + testbench
iverilog -g2012 -o mux4_tb "4:1 mux.v" "4:1 mux_tb"

# Run simulation
vvp mux4_tb

# View waveform
gtkwave mux4_tb.vcd