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1. 4-bit-ALU-with-Scan-Based-DFT-Verification 4-bit-ALU-with-Scan-Based-DFT-Verification Public

   Designed and verified a Scan-Enabled 16-Operation 4-Bit ALU using Verilog HDL. Implemented a 4-stage scan chain using scan flip-flops and developed a self-checking testbench to verify all ALU opera…

   Verilog

2. Clock-Domain-Crossing-CDC-Verification Clock-Domain-Crossing-CDC-Verification Public

   Clock Domain Crossing (CDC) RTL Design, Functional Verification, Self-Checking Testbenches, and Simulation using Verilog HDL.

   Verilog

3. JTAG-IEEE-1149.1-TAP-Controller-Verification JTAG-IEEE-1149.1-TAP-Controller-Verification Public

   Designed and functionally verified a JTAG (IEEE 1149.1) architecture using Verilog HDL. Implemented the TAP Controller, Instruction Register, Instruction Decoder, and Boundary Scan Register to demo…

   Verilog