fix(i2c): saturate I2cMaster timeout counter - #1471
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The timer field is declared as integer range 0 to TIMEOUT_C, but the WAIT_ADDR_ACK_S, WAIT_READ_DATA_S, and WAIT_WRITE_ACK_S states incremented it unconditionally. Because the timeout check compares r.timer against TIMEOUT_C, the increment evaluates TIMEOUT_C+1 one cycle before the timeout is detected, which trips a range violation in VCS simulation (SIMERR_CONSTERR_INDEXEDRANGE). Guard each increment so the counter saturates at TIMEOUT_C. The registered value is unchanged: when the guard blocks the increment, v.timer keeps its default of 0 and the timeout logic also forces 0, so the timeout error still fires on the same clock cycle as before.
ruck314
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August 18, 2026 23:09
This was referenced Aug 23, 2026
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Description
I2cMaster.vhddeclares the FSM timeout counter asinteger range 0 to TIMEOUT_C, but the three waiting states (WAIT_ADDR_ACK_S,WAIT_READ_DATA_S,WAIT_WRITE_ACK_S) incremented it unconditionally. The timeout detection comparesr.timeragainstTIMEOUT_C, so on the cycle the register reaches its maximum the case statement first evaluatesTIMEOUT_C + 1, which is outside the declared range. This aborts VCS simulations of any design that lets an I2C transaction reach its timeout:Each increment is now guarded so the counter saturates at
TIMEOUT_C.