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Release Candidate v4.4.0 #14

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6318a71
updating to latest submodule pre-release branches
ruck314 Aug 24, 2026
9246663
release prep
ruck314 Aug 24, 2026
17c0798
C1100 not required for release
ruck314 Aug 24, 2026
4964fb2
sysmon now included in axi-pcie-core
ruck314 Aug 24, 2026
b04de6b
FW bug fix for latest submodules
ruck314 Aug 24, 2026
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4 changes: 2 additions & 2 deletions firmware/common/kcu1500/rtl/UdpLargeDataBuffer.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -71,13 +71,13 @@ architecture mapping of UdpLargeDataBuffer is
LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C);

constant AXI_RESIZE_16B_C : AxiConfigType := (
ADDR_WIDTH_C => 40, -- Work around to recycle axi-pcie-core FW
ADDR_WIDTH_C => 64,
DATA_BYTES_C => AXI_CONFIG_C.DATA_BYTES_C,
ID_BITS_C => AXI_CONFIG_C.ID_BITS_C,
LEN_BITS_C => AXI_CONFIG_C.LEN_BITS_C);

constant AXI_RESIZE_64B_C : AxiConfigType := (
ADDR_WIDTH_C => 40, -- Work around to recycle axi-pcie-core FW
ADDR_WIDTH_C => 64,
DATA_BYTES_C => MEM_AXI_CONFIG_C.DATA_BYTES_C,
ID_BITS_C => MEM_AXI_CONFIG_C.ID_BITS_C,
LEN_BITS_C => MEM_AXI_CONFIG_C.LEN_BITS_C);
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5 changes: 0 additions & 5 deletions firmware/python/SmurfPcie/SmurfKcu1500RssiOffload10GbE/_Core.py
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Expand Up @@ -132,11 +132,6 @@ def __init__( self,
expand = True,
))

self.add(xil.AxiSysMonUltraScale(
name = 'SysMon',
offset = 0x0010_0000,
))

self.add(EthPhyGrp(
offset = 0x00860000,
expand = True,
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1 change: 0 additions & 1 deletion firmware/releases.yaml
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Expand Up @@ -34,6 +34,5 @@ Releases:
Primary: True
Targets:
- SmurfKcu1500RssiOffload10GbE
- SmurfC1100FebEmu
Types:
- Rogue
2 changes: 1 addition & 1 deletion firmware/submodules/axi-pcie-core
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Submodule axi-pcie-core updated 405 files
2 changes: 1 addition & 1 deletion firmware/submodules/ruckus
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Submodule ruckus updated 93 files
+1 −0 .gitattributes
+11 −11 .github/workflows/conda_build_lib.yml
+9 −9 .github/workflows/conda_build_proj.yml
+8 −8 .github/workflows/conda_build_win.yml
+72 −0 .github/workflows/docker_build.yml
+0 −62 .github/workflows/docker_build_lib.yml
+74 −0 .github/workflows/docs.yml
+2 −2 .github/workflows/gen_release.yml
+2 −14 .github/workflows/ruckus_ci.yml
+13 −1 .gitignore
+136 −0 AGENTS.md
+1 −1 LICENSE.txt
+12 −4 MicroblazeBasicCore/vitis/bit.tcl
+92 −0 MicroblazeBasicCore/vitis/build.py
+42 −23 README.md
+78 −0 cadence/genus/behavioral_verilog.tcl
+5 −2 cadence/genus/syn.tcl
+0 −0 docs/_static/.gitkeep
+30 −0 docs/conf.py
+174 −0 docs/explanation/build_pipeline.rst
+10 −0 docs/explanation/index.rst
+202 −0 docs/explanation/output_artifacts.rst
+110 −0 docs/explanation/overview.rst
+154 −0 docs/explanation/ruckus_tcl_model.rst
+146 −0 docs/how-to/cadence_genus.rst
+119 −0 docs/how-to/dfx_partial_reconfig.rst
+143 −0 docs/how-to/firmware_release.rst
+207 −0 docs/how-to/ghdl_simulation.rst
+22 −0 docs/how-to/index.rst
+112 −0 docs/how-to/microblaze_elf.rst
+129 −0 docs/how-to/segmented_configuration.rst
+143 −0 docs/how-to/synopsys_dc.rst
+468 −0 docs/how-to/vitis_aie.rst
+253 −0 docs/how-to/vitis_hls.rst
+181 −0 docs/how-to/vivado_build.rst
+160 −0 docs/how-to/xsim_rogue_cosim.rst
+28 −0 docs/index.rst
+203 −0 docs/reference/hook_scripts.rst
+13 −0 docs/reference/index.rst
+733 −0 docs/reference/makefile_reference.rst
+482 −0 docs/reference/tcl_api.rst
+5 −0 docs/requirements.txt
+367 −0 docs/tutorial/first_vivado_build.rst
+7 −0 docs/tutorial/index.rst
+0 −48 fabulous/build.tcl
+0 −85 fabulous/proc.tcl
+49 −0 ghdl/analysis.tcl
+30 −10 ghdl/import.tcl
+17 −14 ghdl/load_source_code.tcl
+9 −2 scripts/createNewRepo.py
+15 −1 scripts/firmwareRelease.py
+1 −0 scripts/pip_requirements.txt
+1 −0 scripts/releaseGen.py
+11 −0 scripts/releaseNotes.py
+21 −2 shared/proc.tcl
+16 −1 system_cadence_genus.mk
+0 −159 system_fabulous.mk
+220 −0 system_ghdl.mk
+20 −1 system_shared.mk
+5 −0 system_synopsys_dc.mk
+5 −0 system_vcs.mk
+7 −1 system_vitis_hls.mk
+257 −0 system_vitis_unified_aie.mk
+33 −2 system_vitis_unified_hls.mk
+44 −12 system_vivado.mk
+39 −0 vitis/aie/build.py
+178 −0 vitis/aie/create_proj.py
+106 −0 vitis/aie/emit_partition_conf.sh
+180 −0 vitis/aie/package.sh
+297 −0 vitis/aie/program.sh
+38 −7 vitis/hls/build.py
+2 −6 vitis/hls/create_proj.py
+31 −0 vitis/hls/dcp_rename_ref.tcl
+7 −2 vivado/build.tcl
+3 −0 vivado/env_var.tcl
+30 −0 vivado/gui.tcl
+6 −15 vivado/messages.tcl
+4 −3 vivado/msim.tcl
+4 −2 vivado/pre_synthesis.tcl
+1 −0 vivado/proc.tcl
+109 −0 vivado/proc/SegmentedConfiguration.tcl
+182 −69 vivado/proc/code_loading.tcl
+14 −4 vivado/proc/ip_management.tcl
+25 −12 vivado/proc/output_files.tcl
+62 −13 vivado/proc/project_management.tcl
+75 −1 vivado/proc/sim_management.tcl
+7 −0 vivado/project.tcl
+15 −5 vivado/properties.tcl
+105 −0 vivado/run/pre/xsim.tcl
+28 −2 vivado/sources.tcl
+23 −22 vivado/vcs.tcl
+0 −96 vivado/wis.tcl
+38 −1 vivado/xsim.tcl
2 changes: 1 addition & 1 deletion firmware/submodules/surf
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Submodule surf updated 1605 files
18 changes: 0 additions & 18 deletions firmware/targets/SmurfKcu1500RssiOffload10GbE/hdl/SmurfKcu1500RssiOffload10GbE.vhd
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Expand Up @@ -34,8 +34,6 @@ entity SmurfKcu1500RssiOffload10GbE is
---------------------
-- Application Ports
---------------------
vPIn : in sl;
vNIn : in sl;
-- QSFP[0] Ports
qsfp0RefClkP : in slv(1 downto 0);
qsfp0RefClkN : in slv(1 downto 0);
Expand Down Expand Up @@ -394,22 +392,6 @@ begin
mAxiReadMasters => axilReadMasters,
mAxiReadSlaves => axilReadSlaves);

--------------------------
-- AXI-Lite: SYSMON Module
--------------------------
U_SysMon : entity work.Sysmon
generic map (
TPD_G => TPD_G)
port map (
axiReadMaster => axilReadMasters(0),
axiReadSlave => axilReadSlaves(0),
axiWriteMaster => axilWriteMasters(0),
axiWriteSlave => axilWriteSlaves(0),
axiClk => axilClk,
axiRst => axilReset,
vPIn => vPIn,
vNIn => vNIn);

------------------
-- RSSI/ETH Module
------------------
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4 changes: 2 additions & 2 deletions firmware/targets/shared_config.mk
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@@ -1,5 +1,5 @@
# Define Firmware Version: v4.3.0.0
export PRJ_VERSION = 0x04030000
# Define Firmware Version: v4.4.0.0
export PRJ_VERSION = 0x04040000

# Define release
ifndef RELEASE
Expand Down
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