Skip to content

Add z1015#24

Merged
petergrossmann21 merged 7 commits into
mainfrom
add_z1015
Jun 18, 2026
Merged

Add z1015#24
petergrossmann21 merged 7 commits into
mainfrom
add_z1015

Conversation

@petergrossmann21

@petergrossmann21 petergrossmann21 commented Jun 18, 2026

Copy link
Copy Markdown
Contributor

Summary by CodeRabbit

  • New Features

    • Introduced support for the z1015 eFPGA architecture with comprehensive resource specifications including LUTs, DSPs, BRAMs, and I/O blocks integrated with VPR/Yosys toolchain configuration.
  • Documentation

    • Added complete architecture documentation covering grid dimensions, routing details, CLB structure, memory block organization, and pin constraint conventions.
  • Chores

    • Updated package version to 0.3.0rc1.

@coderabbitai

coderabbitai Bot commented Jun 18, 2026

Copy link
Copy Markdown

Review Change Stack

Warning

Review limit reached

@petergrossmann21, we couldn't start this review because you've reached your PR review rate limit.

More reviews will be available in 52 minutes and 47 seconds. Learn how PR review limits work.

Your organization has used up its prepaid credits, and credit purchases are no longer available. Enable the review add-on in the billing tab to keep reviews running — you're only billed for reviews past your plan's rate limits ($0.25/file).

⌛ How to resolve this issue?

After more reviews become available, a review can be triggered using the @coderabbitai review command as a PR comment. Alternatively, push new commits to this PR.

To avoid repeated limits, reduce automatic review volume by pausing incremental auto-reviews earlier, using label-based review opt-in, excluding WIP or generated PR titles, or requesting reviews manually when the PR is ready. If your team needs uninterrupted high-volume reviews, an organization admin can enable usage-based credits.

🚦 How do rate limits work?

CodeRabbit enforces per-developer PR review limits for each organization. Most developers receive the normal plan refill rate.

For paid Pro and Pro+ PR reviews, CodeRabbit uses adaptive limits for sustained high-volume activity. When a developer's recent PR review activity reaches the 95th percentile or higher among CodeRabbit users, the refill rate gradually slows as usage increases. The highest same-day bursts are limited more strictly.

Please see our Fair Usage Limits Policy for further information.

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 56fead3b-2748-4c59-abad-aa9f2a28f525

📥 Commits

Reviewing files that changed from the base of the PR and between d005f41 and b23ecfc.

📒 Files selected for processing (1)
  • logiklib/zeroasic/z1015/z1015.py
📝 Walkthrough

Walkthrough

Adds a new z1015 eFPGA part driver to logiklib as a LogikFPGA subclass, accompanied by a JSON architecture parameters file specifying grid/routing/CLB/RAM dimensions, a configure_vpr helper that disables VPR image generation, a comprehensive README, and a package version bump to 0.3.0rc1.

Changes

z1015 eFPGA Part Addition

Layer / File(s) Summary
Architecture parameters and z1015 driver class
logiklib/zeroasic/z1015/z1015.json, logiklib/zeroasic/z1015/z1015.py
z1015.json defines FPGA grid sizing, channel counts, CLB/LUT parameters, and RAM/multiplier block geometry. z1015 Python class extends LogikFPGA, registers tool parameters, part metadata, device code, LUT size, clock model, Yosys/VPR macro types, and dataroot file paths for architecture/tech/liberty files.
configure_vpr helper and main entrypoint
logiklib/zeroasic/z1015/z1015.py
configure_vpr(project) locates VPR Place and Route tasks within the project and sets enable_images=False on each. The __main__ block validates file paths via check_filepaths() and writes the manifest JSON.
Architecture README and version bump
logiklib/zeroasic/z1015/README.md, logiklib/__init__.py
README documents z1015 resource inventory, CLB/BLE structure, DSP modes, BRAM configurations, IOB and clock I/O behavior, pin-constraint JSON PCF conventions with a full pin table, and the four-dimensional bitstream mapping index scheme. Package __version__ bumped from 0.2.0 to 0.3.0rc1.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

Poem

🐇 A new chip hops onto the shelf,
z1015, built by itself!
LUTs and BRAMs in a grid so neat,
VPR images off — no crash to beat.
Version bumped, the docs all done,
Another eFPGA part, won! 🎉

🚥 Pre-merge checks | ✅ 5
✅ Passed checks (5 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The title 'Add z1015' directly corresponds to the main change: adding support for the z1015 eFPGA architecture with configuration files, documentation, and a driver module.
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.

✏️ Tip: You can configure your own custom pre-merge checks in the settings.

✨ Finishing Touches
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Commit unit tests in branch add_z1015

Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out.

❤️ Share

Comment @coderabbitai help to get the list of available commands and usage tips.

@coderabbitai coderabbitai Bot left a comment

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Actionable comments posted: 4

🧹 Nitpick comments (1)
logiklib/zeroasic/z1015/README.md (1)

140-145: 💤 Low value

Remove trailing pipes for table style consistency.

The bitstream mapping table has trailing pipes, but the project markdown style expects no leading or trailing pipes.

♻️ Proposed fix
-Index       | Min  | Max                          |
------------|------|------------------------------|
-X           | 0    | 93        |
-Y           | 0    | 93        |
-Address     | 0    | 310        |
-Bit Index   | 0    | 7  |
+Index       | Min  | Max
+------------|------|------------------------------
+X           | 0    | 93
+Y           | 0    | 93
+Address     | 0    | 310
+Bit Index   | 0    | 7
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@logiklib/zeroasic/z1015/README.md` around lines 140 - 145, Remove the
trailing pipe characters from the end of each row in the bitstream mapping table
in the README.md file. The table currently has pipes at the end of every row
(header, separator, and data rows including X, Y, Address, and Bit Index), but
the project markdown style expects no leading or trailing pipes. Delete the
rightmost pipe from each of these rows to match the expected formatting
convention.

Source: Linters/SAST tools

🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@logiklib/zeroasic/z1015/README.md`:
- Around line 100-105: The fenced code block in the README.md file is missing
the language specifier for syntax highlighting. Add `json` immediately after the
opening triple backticks (```) on the line before the "foo" property definition
to properly indicate this is a JSON code block, which will enable correct syntax
highlighting in the rendered documentation.

In `@logiklib/zeroasic/z1015/z1015.py`:
- Line 50: Multiple lines in the file exceed the 120-character limit and need to
be wrapped for compliance with the project's style guidelines. For the
`set_yosys_dsptechmap` call on line 50 and the similar method calls on lines
55-56, 58-59, and 61-62, break the long parameter lists across multiple lines
with proper indentation. Each wrapped line should start the parameter list on a
new indented line, keeping related parameters grouped logically and ensuring no
single line exceeds 120 characters.
- Line 9: Remove the unused `import os.path` statement from the z1015.py file.
The import statement is not being utilized anywhere in the code and is causing a
flake8 compliance issue. Simply delete this line to resolve the unused import
warning.
- Around line 110-113: The variable fpga in the __main__ block is assigned the
class z1015 itself rather than an instance of it. The subsequent calls to
check_filepaths() and write_manifest() are instance methods and cannot be called
on the class. Fix this by instantiating the z1015 class by changing fpga = z1015
to fpga = z1015() so that fpga becomes an instance object with access to the
required instance methods.

---

Nitpick comments:
In `@logiklib/zeroasic/z1015/README.md`:
- Around line 140-145: Remove the trailing pipe characters from the end of each
row in the bitstream mapping table in the README.md file. The table currently
has pipes at the end of every row (header, separator, and data rows including X,
Y, Address, and Bit Index), but the project markdown style expects no leading or
trailing pipes. Delete the rightmost pipe from each of these rows to match the
expected formatting convention.
🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

  • Push a commit to this branch (recommended)
  • Create a new PR with the fixes

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 60750dab-6996-42ee-b5a3-ec15feb6dbe7

📥 Commits

Reviewing files that changed from the base of the PR and between 134c324 and d005f41.

📒 Files selected for processing (4)
  • logiklib/__init__.py
  • logiklib/zeroasic/z1015/README.md
  • logiklib/zeroasic/z1015/z1015.json
  • logiklib/zeroasic/z1015/z1015.py

Comment on lines +100 to +105
```
"foo": {
"direction": "input",
"pin": "gpio_in_east[17]"
},
```

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ Potential issue | 🟡 Minor | ⚡ Quick win

Add language specifier to code block.

The fenced code block should specify json for proper syntax highlighting.

📝 Proposed fix
-```
+```json
   "foo": {
     "direction": "input",
     "pin": "gpio_in_east[17]"
   },
 ```
🧰 Tools
🪛 markdownlint-cli2 (0.22.1)

[warning] 100-100: Fenced code blocks should have a language specified

(MD040, fenced-code-language)

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@logiklib/zeroasic/z1015/README.md` around lines 100 - 105, The fenced code
block in the README.md file is missing the language specifier for syntax
highlighting. Add `json` immediately after the opening triple backticks (```) on
the line before the "foo" property definition to properly indicate this is a
JSON code block, which will enable correct syntax highlighting in the rendered
documentation.

Source: Linters/SAST tools

Comment thread logiklib/zeroasic/z1015/z1015.py Outdated
Comment thread logiklib/zeroasic/z1015/z1015.py Outdated
Comment on lines +110 to +113
if __name__ == "__main__":
fpga = z1015
assert fpga.check_filepaths()
fpga.write_manifest(f'{fpga.design}.json')

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ Potential issue | 🔴 Critical | ⚡ Quick win

Instantiate the class before calling instance methods.

Line 111 assigns the class z1015 instead of creating an instance. Calling check_filepaths() and write_manifest() on a class (rather than an instance) will raise AttributeError at runtime unless these are classmethods, which is unlikely for device driver APIs.

🐛 Proposed fix
 if __name__ == "__main__":
-    fpga = z1015
+    fpga = z1015()
     assert fpga.check_filepaths()
     fpga.write_manifest(f'{fpga.design}.json')
📝 Committable suggestion

‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.

Suggested change
if __name__ == "__main__":
fpga = z1015
assert fpga.check_filepaths()
fpga.write_manifest(f'{fpga.design}.json')
if __name__ == "__main__":
fpga = z1015()
assert fpga.check_filepaths()
fpga.write_manifest(f'{fpga.design}.json')
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@logiklib/zeroasic/z1015/z1015.py` around lines 110 - 113, The variable fpga
in the __main__ block is assigned the class z1015 itself rather than an instance
of it. The subsequent calls to check_filepaths() and write_manifest() are
instance methods and cannot be called on the class. Fix this by instantiating
the z1015 class by changing fpga = z1015 to fpga = z1015() so that fpga becomes
an instance object with access to the required instance methods.

@petergrossmann21 petergrossmann21 merged commit 5237d0d into main Jun 18, 2026
4 checks passed
@petergrossmann21 petergrossmann21 deleted the add_z1015 branch June 19, 2026 16:03
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant