sylva-components

RTL hardware components that compose the full system, at the RTL level, for the Sylva Application-Level Synthesis (ALS) flow of the SiLago framework.

Sylva (the sylva-suite EDA tool) maps a data-streaming application — modelled as a Homogeneous Synchronous Dataflow (HSDF) graph — onto a network of pre-characterised hardware blocks. This repository holds those blocks: the building-block RTL components and the integration modules that assemble them into AlImps and a complete host system.

Concepts

Term	Meaning
ALS	Application-Level Synthesis — the synthesis level above HLS, which maps an application graph onto hardware.
AlImp	Algorithm Implementation — one or more DRRA cells implementing one algorithm (graph node); produced by the Vesyla HLS tool.
DRRA	Dynamically Reconfigurable Resource Array — the CGRA compute fabric inside an AlImp.
GLIC	Global Interconnect and Control.
IB / OB	Input Buffer / Output Buffer.
TLB / AGU	Translation Lookaside Buffer / Address Generation Unit.

Architecture in one picture

An application runs as a network of AlImps orchestrated by a host system. The host (a PicoRV32 CPU, a bootloader, an AXI-Lite master and a 64-bit global timer) loads programs from external memory and starts each AlImp at a precise, statically scheduled cycle. Data moves directly between AlImps:

sending DRRA → OB → Transporter → IB → receiving DRRA

Each buffer uses a TLB/AGU for virtual→physical address translation, and a per-AlImp synchroniser releases the processor and the transporters at the scheduled global-timer cycle, giving cycle-accurate, deterministic execution.

Layout

components/     # reusable leaf RTL blocks
integration/    # modules that compose the blocks into AlImps and a system

Components

Component	Purpose
processor	PicoRV32 RISC-V CPU (host and per-AlImp).
axi_lite_master	Native-memory → AXI-Lite master.
axi_lite_slave	AXI-Lite slave → native memory, per-AlImp endpoint.
bootloader	Copies host program/data from external memory.
booter	Releases an AlImp CPU from reset.
peripherals	AlImp peripheral interface (decoder, loaders, AGUs, call/return).
synchroniser	Static-schedule timing (stall CPU, start transporters).
datamover	IB/OB/transporter composition wrappers.
buffer	RF / SRAM / FIFO data buffers.
tlb	Address translation (table TLB, AGU, dummy).
transporter	Programmable data-movement engine + ISA.
sram	1-clock and 2-clock SRAM macros.

Integration

Module	Purpose
integration/utils	Shared packages and interfaces.
integration/alimp	A complete AlImp processing element.
integration/system	Host + AlImp network (top level).

See integration/component_map.md for the global address map.

Build

The repository uses Bender for dependency management; each component carries a Bender.yml manifest. RTL is written in SystemVerilog, except the PicoRV32 core (Verilog). It is consumed as a git submodule by sylva-suite, whose Assembly stage generates the per-application configuration for these components.

Documentation

Conceptual and tool documentation lives in the SiLago documentation under ToolChain → Sylva ALS.