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feat: add in-memory LRU+TTL cache for validation results - #1933

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nissessenap wants to merge 5 commits into
sigstore:mainfrom
nissessenap:cache_impl
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feat: add in-memory LRU+TTL cache for validation results#1933
nissessenap wants to merge 5 commits into
sigstore:mainfrom
nissessenap:cache_impl

feat: add cache hit/miss debug logging and e2e test resources

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DCO / DCO succeeded Feb 16, 2026 in 0s

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