Implementation of a complete Design-for-Test (DFT) flow using Cadence Modus on ISCAS'89 benchmark circuits, including scan insertion, ATPG, fault simulation, and test quality analysis.
This project demonstrates the implementation of a standard industrial Design-for-Test (DFT) flow using Cadence Modus. ISCAS'89 sequential benchmark circuits were used to evaluate scan insertion, Automatic Test Pattern Generation (ATPG), and fault coverage.
The objective was to understand the complete production-level DFT methodology used in modern ASIC design.
- Perform scan insertion using Cadence Modus
- Generate ATPG patterns
- Perform fault simulation
- Evaluate fault coverage
- Analyze DFT reports
- Study industrial DFT implementation flow
RTL / Netlist
↓
Design Rule Check (DRC)
↓
Scan Insertion
↓
Scan Chain Stitching
↓
ATPG
↓
Fault Simulation
↓
Coverage Analysis
↓
DFT Reports
- ISCAS'89 benchmark circuits
- Cadence Modus DFT flow
- Scan insertion
- ATPG generation
- Fault simulation
- Fault coverage analysis
- Industrial DFT methodology
- Cadence Modus
- Verilog HDL
iscas89-dft-modus/
├── rtl/
├── scripts/
├── reports/
├── patterns/
├── images/
├── docs/
└── README.md
The repository contains:
- Scan insertion reports
- ATPG reports
- Fault coverage reports
- DFT logs
- Generated test patterns
- Cadence Modus Documentation
- ISCAS'89 Benchmark Suite
Shrisha R Katti
Dibyadyuti Mohanty
Disha Dash
Tejashree S
Manas Kole
Electronics and Communication Engineering
PES University