📡 UART Communication with 16× Oversampling & Hamming (7,4) Error Correction Code

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📌 Overview

This project implements a high-reliability UART Transceiver System in Verilog HDL, designed for FPGA target architectures. To overcome common serial communication failure modes in noisy hardware environments, the design incorporates:

1. 16× Oversampling Noise Filter & Clock Recovery Engine: Eliminates clock skew and filters out high-frequency noise spikes on the RX line by sampling each bit period 16 times and taking center-majority decisions.
2. Hamming (7,4) Single Error Correction (SEC) & Parity Engine: Automatically detects and corrects single-bit corruption errors in real-time without requiring retransmission.

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📊 Project Technical Report & Presentation Showcase

Important

📥 Official Technical Project Report & Presentation Documentation:

• 📄 Complete Project Report (DOCX): uart-hamming/reports/mini_project.docx (Comprehensive project document detailing RTL design, testbenches, mathematical error-correction theory, and Vivado synthesis results)

📑 Project Document & Presentation Breakdown

Section #	Document Topic	Technical Content Highlighted
01	Introduction & Problem Statement	Overview of UART asynchronous transmission vulnerabilities in noisy industrial channels.
02	16x Oversampling Architecture	Mathematical principle of mid-cycle sampling (ticks 7, 8, 9) for clock recovery and noise rejection.
03	Hamming (7,4) SEC Theory	Parity matrix generation, generator polynomials, and syndrome bit calculation ($s_1, s_2, s_3$).
04	Verilog RTL Modules	Functional breakdown of baud_gen, oversample_gen_16x, hamming_encoder, uart_tx_hamming, uart_rx_hamming, and hamming_decoder.
05	Simulation Waveforms	Testbench setup, timing diagrams, and fault injection verification (ModelSim & Xilinx Vivado).
06	Hardware Synthesis & FPGA Results	Resource utilization (LUTs, Flip-Flops), maximum clock frequency ($F_{max}$), and timing closure.

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🏗️ System Architecture & RTL Block Diagram

graph LR
    subgraph Transmitter Subsystem
        DATA_IN[8-Bit Parallel Input] --> ENC[Hamming Encoder]
        ENC -->|12-Bit Codeword| TX_FSM[UART TX FSM]
        CLK[System Clock] --> BAUD[Baud Rate Generator]
        BAUD -->|Baud Tick| TX_FSM
        TX_FSM -->|Serial Line| TX_PIN[TX Pin]
    end

    subgraph Physical Channel
        TX_PIN -->|Serial Channel / Noise| RX_PIN[RX Pin]
    end

    subgraph Receiver Subsystem
        RX_PIN --> RX_FSM[UART RX FSM]
        CLK --> OS[16x Oversampling Gen]
        OS -->|Sample Tick| RX_FSM
        RX_FSM -->|Received Codeword| DEC[Hamming Decoder]
        DEC --> DATA_OUT[8-Bit Data Out]
        DEC --> ERR_DET[Error Detected Flag]
        DEC --> ERR_CORR[Error Corrected Flag]
    end

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🔬 Core RTL Modules Breakdown

Module File	Description & Functionality
uart_hamming_top.v	Top-level integration module connecting Baud Generator, Oversampling Generator, Hamming Encoder/Decoder, and UART Transceiver modules.
baud_gen.v	Configurable frequency divider generating exact baud rate ticks (e.g. 9600 / 115200 bps from 50MHz/100MHz clock).
oversample_gen_16x.v	Generates a 16× frequency tick per bit period for precise mid-bit sampling.
hamming_encoder.v	Encodes 8-bit input data into two 4-bit nibbles, appending 3 parity bits ($p_1, p_2, p_3$) per nibble to create a (7,4) Hamming codeword structure.
uart_tx_hamming.v	Finite State Machine (FSM) managing START bit, 12-bit Hamming payload transmission, and STOP bit.
uart_rx_16x.v / uart_rx_hamming.v	Finite State Machine (FSM) sampling RX line 16 times per bit cycle. Majority voting logic selects mid-cycle sample values (ticks 7, 8, 9) for high noise immunity.
hamming_decoder.v	Computes syndrome vector $S = [s_1, s_2, s_3]$. Identifies corrupt bit location, flips the bit back to correct state, and asserts error_detected and error_corrected output signals.

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🧮 Mathematical Principle: Hamming (7,4) Code

The Hamming (7,4) code encodes 4 data bits ($d_1, d_2, d_3, d_4$) into 7 code bits by generating 3 parity bits ($p_1, p_2, p_3$):

$$p_1 = d_1 \oplus d_2 \oplus d_4$$ $$p_2 = d_1 \oplus d_3 \oplus d_4$$ $$p_3 = d_2 \oplus d_3 \oplus d_4$$

Syndrome Matrix & Error Correction

Upon reception, the decoder computes the syndrome bits: $$s_1 = p_1 \oplus d_1 \oplus d_2 \oplus d_4$$ $$s_2 = p_2 \oplus d_1 \oplus d_3 \oplus d_4$$ $$s_3 = p_3 \oplus d_2 \oplus d_3 \oplus d_4$$

• If $S = [0, 0, 0]$: No error detected.
• If $S \neq [0, 0, 0]$: Syndrome value directly points to the corrupted bit index, which is inverted to restore exact data integrity.

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📁 Repository Directory Hierarchy

UART_COM/
└── uart-hamming/
    ├── reports/
    │   └── mini_project.docx      # Official Project Technical Report & Documentation
    ├── src/
    │   ├── uart_hamming_top.v     # Top-Level Integration
    │   ├── baud_gen.v             # Baud Rate Generator
    │   ├── oversample_gen_16x.v   # 16x Oversampling Clock Generator
    │   ├── hamming_encoder.v      # (7,4) Hamming Encoder
    │   ├── hamming_decoder.v      # Hamming Decoder & SEC Error Corrector
    │   ├── uart_tx_hamming.v      # UART Transmitter FSM
    │   ├── uart_rx_hamming.v      # UART Receiver FSM
    │   ├── uart_tx.v              # Standard UART Transmitter
    │   └── uart_rx_16x.v          # 16x Oversample UART Receiver
    ├── simulation/                # Testbenches & Simulation Waveform Configs
    └── images/                    # RTL Schematics & Waveform Screenshots

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⚙️ Simulation & Verification Guide

Running Simulation in Xilinx Vivado / ModelSim

1. Open Vivado or ModelSim and create a new RTL project.
2. Add all Verilog source files from uart-hamming/src/.
3. Set uart_hamming_top.v as the top module (or load testbench from simulation/).
4. Run Behavioral Simulation for 10 ms.
5. Observe waveforms:
   • Verify tx_pin serial data stream with 16x sampling ticks.
   • Force a 1-bit noise inversion on tx_pin line.
   • Confirm error_detected and error_corrected signals toggle high, and data_out matches original data_in.

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📜 License

Distributed under the MIT License.

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Developed by A Sharath — ECE Placement Portfolio