⚡ Hardware Implementation of DFT & IDFT Co-Processor (ASIC & FPGA Synthesis Flow)

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📌 Overview

This project implements a hardware-optimized Discrete Fourier Transform (DFT) and Inverse Discrete Fourier Transform (IDFT) co-processor designed in Verilog HDL and synthesized through a full ASIC Physical Design flow (Cadence Genus Synthesis and Cadence Innovus Implementation System 20.14).

The architecture features a 16-bit fixed-point Radix-2 Butterfly Structure, a Complex Multiplier-Accumulator (MAC) Engine, custom Synopsys Design Constraints (SDC), and complete On-Chip Variation (OCV) / CPPR Post-Route Static Timing Analysis (STA).

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🧮 Mathematical Foundations

1. Discrete Fourier Transform (DFT)

Converts a discrete time-domain sequence $x[n]$ of length $N$ into its complex frequency-domain representation $X[k]$:

$$X[k] = \sum_{n=0}^{N-1} x[n] \cdot W_N^{kn} = \sum_{n=0}^{N-1} x[n] \left[ \cos\left(\frac{2\pi kn}{N}\right) - j \sin\left(\frac{2\pi kn}{N}\right) \right]$$

2. Inverse Discrete Fourier Transform (IDFT)

Synthesizes the original time-domain sequence $x[n]$ from its complex frequency-domain components $X[k]$:

$$x[n] = \frac{1}{N} \sum_{k=0}^{N-1} X[k] \cdot W_N^{-kn} = \frac{1}{N} \sum_{k=0}^{N-1} X[k] \left[ \cos\left(\frac{2\pi kn}{N}\right) + j \sin\left(\frac{2\pi kn}{N}\right) \right]$$

where $W_N^{kn} = e^{-j\frac{2\pi}{N}kn}$ represents the complex Twiddle Factor.

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🏗️ Hardware Architecture & RTL Block Diagram

graph TD
    subgraph Input & Twiddle Factor Generator
        IN[Discrete Input Vector x[n]] --> MAC[Complex MAC Engine]
        TW[Twiddle Factor ROM LUT - cos / sin] --> MAC
    end

    subgraph Core Processing Engines
        MAC --> DFT[DFT Computation Unit]
        MAC --> IDFT[IDFT Reconstruction Unit]
    end

    subgraph Spectral Output & Verification
        DFT --> SPECTRUM[Frequency Spectrum X[k]]
        IDFT --> RECON[Reconstructed Time Signal x[n]]
        SPECTRUM --> COMP[Magnitude & Phase Verification]
    end

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💻 Source Code & Scripts Directory

• 📜 Verilog RTL Code: rtl/fft.v — Fixed-point 16-bit Radix-2 Butterfly & Complex Multiplier module.
• ⚙️ Synthesis Script: scripts/synthesis.tcl — Cadence Genus / Synopsys TCL synthesis commands and optimization flags.
• ⏱️ Timing Constraints: constraints/fft.sdc — SDC file defining 500 MHz (2ns period) clock and I/O delays.
• 📐 Physical Design Specs: docs/INNOVUS_PHYSICAL_DESIGN.md — Cadence Innovus floorplanning, MMMC setup, CTS, and PnR flow.

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🖼️ Verification & ASIC Layout Gallery

Below are the lab photos, synthesized layouts, and physical design flow notes stored in assets/gallery/:

Asset Name	Category	Description
01_genus_synthesis_tcl_script.jpeg	Synthesis	TCL script for Cadence Genus library search paths & timing reports.
02_synopsys_sdc_timing_constraints.jpeg	Constraints	SDC timing constraints (create_clock -period 2, input/output delays).
03_physical_design_mmmc_setup_notes.jpeg	Physical Design	MMMC (Multi-Mode Multi-Corner) library set & LEF setup notes.
04_delay_corners_analysis_views_notes.jpeg	STA	Worst-case & best-case delay corner analysis views setup.
05_floorplanning_and_pin_placement_notes.jpeg	Floorplanning	Square die aspect ratio, power routing, and I/O pin placement.
06_cts_and_nano_route_notes.jpeg	CTS & Routing	Clock Tree Synthesis skew optimization & NanoRoute rules.
07_ocv_cppr_post_route_sta_notes.jpeg	Signoff STA	On-Chip Variation (OCV) and CPPR post-route timing closure.
08_innovus_full_asic_layout_routing.jpeg	ASIC Layout	Cadence Innovus full standard cell placement & Metal1-Metal4 routing.
09_innovus_power_ring_and_io_pins.jpeg	ASIC Layout	VDD/VSS power ring grid & peripheral I/O pin layout.
10_verilog_fft_butterfly_code_close_up.jpeg	Verilog Code	Close-up photo of fft.v complex multiplication & butterfly logic.
11_verilog_fft_code_gedit_editor.jpeg	Verilog Code	Full Gedit editor view of fft.v source code.
12_verilog_fft_endmodule_editor_view.jpeg	Verilog Code	Gedit editor view showing endmodule termination lines.

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📜 License

Distributed under the MIT License.

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Developed by A Sharath — ECE Placement Portfolio