spinalhdl-xilinx-components

A code generator that reads Xilinx VCOMP VHDL component declaration files and produces SpinalHDL BlackBox wrapper classes.

Building

sbt compile

Usage

sbt "run <command> [options] [file]"

If [file] is omitted, the tool reads from stdin.

Commands

Command	Description
generate	Parse VHDL and emit SpinalHDL BlackBox classes
list	Print the names of all matching components

Options

Flag	Default	Description
-p, --package <pkg>	xilinx.unisim	Scala package name for generated output
-f, --filter <regex>	.*	Only include components whose name matches. Repeatable.
-s, --split	off	Write one .scala file per component instead of stdout

Example

Given this VHDL component declaration (excerpt from a Xilinx VCOMP file):

library IEEE;
use IEEE.STD_LOGIC_1164.all;
package UNISIM_VCOMP is

  component FIFO36E2
    generic (
      CASCADE_ORDER    : string  := "NONE";
      DATA_WIDTH       : integer := 4;
      PROG_FULL_THRESH : integer := 256;
      READ_WIDTH       : integer := 4;
      WRITE_WIDTH      : integer := 4
    );
    port (
      RDCLK  : in  std_logic;
      WRCLK  : in  std_logic;
      RST    : in  std_logic;
      DIN    : in  std_logic_vector(63 downto 0);
      DINP   : in  std_logic_vector(7 downto 0);
      DOUT   : out std_logic_vector(63 downto 0);
      EMPTY  : out std_logic;
      FULL   : out std_logic
    );
  end component FIFO36E2;

end UNISIM_VCOMP;

Run:

sbt "run generate -p xilinx.unisim components.vhd"

Output:

package xilinx.unisim

import spinal.core._

class FIFO36E2(
    CASCADE_ORDER: String = "NONE",
    DATA_WIDTH: Int = 4,
    PROG_FULL_THRESH: Int = 256,
    READ_WIDTH: Int = 4,
    WRITE_WIDTH: Int = 4
) extends BlackBox {

  val generic = new Generic {
    val CASCADE_ORDER = FIFO36E2.this.CASCADE_ORDER
    val DATA_WIDTH = FIFO36E2.this.DATA_WIDTH
    val PROG_FULL_THRESH = FIFO36E2.this.PROG_FULL_THRESH
    val READ_WIDTH = FIFO36E2.this.READ_WIDTH
    val WRITE_WIDTH = FIFO36E2.this.WRITE_WIDTH
  }

  val io = new Bundle {
    val RDCLK = in(Bool())
    val WRCLK = in(Bool())
    val RST = in(Bool())
    val DIN = in(Bits(64 bits))
    val DINP = in(Bits(8 bits))
    val DOUT = out(Bits(64 bits))
    val EMPTY = out(Bool())
    val FULL = out(Bool())
  }

  noIoPrefix()
}

Common workflows

Generate all components from a VCOMP file to stdout:

sbt "run generate -p xilinx.unisim unisim_VCOMP.vhd"

Generate only FIFO components, one file each:

sbt "run generate -p xilinx.unisim -f FIFO -s unisim_VCOMP.vhd"

List all component names:

sbt "run list unisim_VCOMP.vhd"

List components matching a pattern:

sbt "run list -f BUF unisim_VCOMP.vhd"

Generate from XPM primitives with a different package:

sbt "run generate -p xilinx.xpm xpm_VCOMP.vhd"

Type mapping

VHDL type	SpinalHDL type
std_logic, bit (port)	Bool()
std_logic_vector(N-1 downto 0) (port)	Bits(N bits)
inout std_logic (port)	Analog(Bool())
inout std_logic_vector(N-1 downto 0) (port)	Analog(Bits(N bits))
integer (generic)	Int
real (generic)	Double
boolean (generic)	Boolean
string (generic)	String
std_logic (generic)	Char

Port widths that are constant expressions (e.g. 63 downto 0) are evaluated at generation time. Widths that reference generic parameters (e.g. DATA_WIDTH-1 downto 0) are emitted as Scala expressions.