Parameterized Serial Router — RTL & UVM Verification

A cycle-compatible 16×16 serial router implemented in synthesizable, parameterized SystemVerilog and verified with a reusable UVM 1.2 environment. The repository combines a frozen behavioral baseline, modern explicit-grant RTL, protocol assertions, differential checking, functional and code coverage, and a detector-qualified mutation campaign.

Verified results

Verification gate	Result
Full regression	111/111 runs passed
Directed tests + randomized stress	11 + 100 recorded seeds
Source/destination routes	256/256 covered
Planned functional coverage	1,731/1,731 bins (100%)
Modern RTL statement coverage	95.55%
Modern RTL toggle coverage	100%
Reviewed branch / FSM coverage	100% / 100%
Differential comparison	0 cycle mismatches
Mutation analysis	13/13 faults detected

The raw and reviewed coverage counts, exclusions, and reproduction evidence are documented in docs/results.md and results/signoff-summary.json.

Architecture

flowchart LR
    SRC["16 serial sources"] --> IF["Per-source header and packet state"]
    IF --> REQ["Request matrix"]
    REQ --> ARB["Rotating-priority arbitration"]
    ARB --> OWN["Packet-held destination ownership"]
    OWN --> MUX["Registered output multiplexers"]
    MUX --> DST["16 serial destinations"]

    MON["Input and output monitors"] --> REF["Independent reference model"]
    REF --> SB["Destination-ordered scoreboard"]
    SRC -. "UVM stimulus" .-> IF
    MUX -. "Assertions and coverage" .-> MON

Loading

The default router #(.NUM_PORTS(16)) preserves the baseline pin interface and observed cycle timing while replacing internal tri-state buses with explicit requests, grants, ownership registers, and output multiplexing. NUM_PORTS must be a power of two, and the destination width is derived with $clog2(NUM_PORTS).

Packets contain an LSB-first destination, a required route marker, four routing settling clocks, and 1–64 payload bytes. Payload advances only when valid_n == 0 && busy_n == 1; frame_n rises with the final accepted bit.

Verification methodology

• One active UVM source agent per input and passive monitoring at every output
• Monitor-derived expectations and an independent routing/arbitration model
• Exact route, length, data, ordering, loss, duplication, timeout, and latency checks
• Public-interface and internal-RTL SystemVerilog assertions
• Directed route, pattern, length, spacing, contention, fairness, reset, and error tests
• One hundred reproducible constrained-random stress seeds
• Cycle-by-cycle comparison against the frozen behavioral baseline
• Thirteen compile-selected mutations covering data, routing, framing, timing, flow control, and starvation faults

Production RTL has no fault controls. Mutation logic is isolated under rtl/mutations and selected only through a simulation wrapper.

Quick start

Requirements are Windows PowerShell and QuestaSim 2024.1 with its bundled UVM 1.2 installation. The simulator installation is resolved in this order: -QuestaHome, QUESTA_HOME, then C:\questasim64_2024.1.

git clone https://github.com/rohan-js/serial-router-uvm-verification.git
Set-Location serial-router-uvm-verification

# Baseline compatibility smoke
.\run.ps1 -Test smoke_test -Seed 1 -Dut modern

# Explicit simulator installation
.\ci.ps1 -Rebuild -QuestaHome 'C:\questasim64_2024.1'

Useful commands:

# Individual runs
.\run.ps1 -Test contention_test -Seed 42 -Dut modern -Coverage -Wave
.\run.ps1 -Test smoke_test -Seed 1 -Dut legacy
.\run.ps1 -Test smoke_test -Seed 1 -Dut mutation:bit_flip

# Regression profiles
.\regress.ps1 -Profile smoke -Coverage
.\regress.ps1 -Profile full -Coverage
.\regress.ps1 -Profile mutation

# Complete local gates
.\ci.ps1
.\ci.ps1 -Full

Each run creates a timestamped directory under results/runs containing its transcript, stable JSON/JUnit result, seed and DUT identity, and optional UCDB or WLF artifacts. Generated work libraries, transcripts, waves, and coverage databases are ignored; curated summaries remain versioned. Passing waves are removed unless -Wave or -Gui is requested, while failure waves are retained.

GitHub-hosted automation is intentionally omitted because the validated flow depends on a locally licensed QuestaSim installation.

Engineering documentation

• Serial protocol specification
• RTL and UVM architecture
• Verification plan
• Requirements traceability
• Coverage plan
• Mutation plan
• Reproducible results
• Engineering report

Baseline integrity and use notice

legacy/original is a byte-identical, immutable behavioral baseline whose SHA-256 values are recorded in legacy/MANIFEST.sha256. The derived copy only renames modules so both implementations can be compiled side by side.

This repository is publicly viewable, but no reuse license is granted. The frozen baseline is explicitly excluded from any implied permission or grant.