Interrupts

The purpose of this page is to document how interrupts work on this processor.

In CP0 there are 3 main registers which are used for interrupts. Register 12, 13, and 14, below is a list of what each register contains. An ISR can be placed at one of two addresses, 0x180 or 0x200. The first is the general purpose ISR and should be used for any code generated for this project. There are only two instructions to interact with CP0. Move from Co-processor 0 (MFC0) and Move to Co-processor 0 (MTC0). These instructions are word only and are considered modified R type instructions, this means that this is a register to register transfer.

• Register 12 - This register enables and disables interrupts. Each individual enable/disable as well as the master is located here.
• Register 13 - This register contains the exception code as well as the flags for what interrupt has been triggered.
• Register 14 - This register stores the return address that will need to be restored.

On system startup write the following to initialize the system. This disables interrupts.

MTC0 $zero, $12
MTC0 $zero, $13
MTC0 $zero, $14

To enable interrupts you must use register 12 to configure the co-processor. Bit 0 is the enable master, and bits 15 through 10 are to enable each individual interrupt vector seperatly. Bits 9 and 8 are trap enables. To use Trap Not Equal (TNE) or Trap Equal (TEQ) you must enable bit 8. To enable traps, the timer interrupt, and the encryption accelerator interrupt a register with the following value must be loaded into register 12 of the co-processor.

0x8501h

When an interrupt is received the value of the return address is saved in register 14 and the address of the ISR that is being used is loaded into the PC counter. The following is psuedocode on how and what to do in the ISR

MFC0 MIPS register, $12
//subtract the saved value by 1 to disabled interrupts
MTC0 MIPS register, $12
MFC0 MIPS register, $13
//Look at the exception code to figure out if it is a trap or interrupt. 0x00h is interrupt, 0x0Dh is Trap, 0x10h is nothing pending
//bits 8 and 9 are the trap bits, bits 10 though 15 are interrupts.
//depending on what you figured out is needing service, service it.
//when done servicing it get ready to return from it
MFC0 MIPS register, $12
//to clear serviced interrupt set individual pin enable flag to zero
MTC0 MIPS register, $12
MFC0 MIPS register, $12
//re-enable the individual pin that was serviced as well the master interrupt enable (bit zero)
MFC0 MIPS register, $14 //this is the return address
MTC0 MIPS register, $12
JR MIPS register //this was loaded from co-processor register 12.

This should end the ISR and covers how to save properly interact with the co-processor during an interrupt. This document makes no assumption on what else might need to be saved once in the interrupt or needs to be loaded before returning.