OpenTestability

OpenTestability is an open-source DFT toolkit for gate-level circuits. It combines testability analysis (COP/SCOAP), reconvergence-aware scoring, and automated test point insertion (TPI) in one workflow.

Why OpenTestability

• practical TPI flow from metrics to enhanced Verilog
• native Yosys JSON workflow from metrics to enhanced netlist
• reconvergence-aware analysis for better observability estimates
• verbose reporting and reproducible logs for debug and benchmarking
• FaultFlow integration: provides reconvergence structural data with Yosys net IDs for ATPG fault ordering

Quick Start

Linux is the recommended environment (macOS is also supported).

git clone https://github.com/ranaumarnadeem/OpenTestability.git
cd OpenTestability

python3 -m venv venv
source venv/bin/activate
pip install -r requirements.txt
pip install -e .          # compiles the Cython SCOAP kernel

Or with Nix (no clone, no venv):

nix run github:ranaumarnadeem/OpenTestability -- scoap -i design.json -j
nix profile install github:ranaumarnadeem/OpenTestability   # persistent `opentest`

Run a first command (the repo ships a small s27 netlist to try):

python3 opentest scoap -i data/input/s27.json -j

Developer Quick Start

# Linux/macOS (or `nix develop` for a one-command reproducible shell)
source venv/bin/activate

# Run tests
pytest tests/ -v

# Run fast smoke tests
pytest tests/ -m smoke -v

For detailed developer testing workflow, see Developer Test Suite Guide.

Project Structure

OpenTestability/
|-- opentest
|-- src/opentestability/
|   |-- core/
|   |-- parsers/
|   |-- yosys/
|   |-- visualization/
|   `-- utils/
|-- docs/
|-- tests/
|   |-- unit/
|   |-- integration/
|   |-- system/
|   `-- fixtures/
|-- data/
|   |-- input/
|   |-- parsed/
|   |-- dag_output/
|   |-- reconvergence_output/
|   |-- results/
|   `-- TPI/
|-- results/
|   |-- log/
|   `-- reports/
`-- output/

Commands

Command	What it does
scoap	SCOAP testability metrics on a Yosys JSON netlist
cop	COP probabilistic testability metrics on a Yosys JSON netlist
analyze_and_add_tp	Full TPI pipeline: metrics → scoring → test-point insertion

analyze_and_add_tp accepts --tech sky130|osu035|ihp|nangate|auto to select the PDK cell library used for test point insertion, and -r to enable reconvergence-aware metric computation.

Common Workflows

python3 opentest scoap -i <design.json> -j
python3 opentest analyze_and_add_tp -i <design.json> --scoap -r -t 50 -m 10 --tech sky130 -v

DFT Flow

Documentation Map

• Documentation Home
• Getting Started
• Test Point Insertion Guide
• Examples
• Command Reference
• Algorithms Summary
• Reconvergence Integration
• FaultFlow Preflight Protocol
• Developer Architecture Guide
• Developer Test Suite Guide
• API Overview
• SCOAP API

Future Plans

1. Add better algorithms and handling for reconvergent fanouts, including BDD and Bayesian-theorem-inspired approaches.
2. Add stronger parallelism for faster computation on large designs.
3. Improve report format and readability for analysis and TPI outputs.
4. Add a dedicated developer debug mode for deeper troubleshooting.
5. Deepen FaultFlow integration: Phase B structural pre-certification of canceling-path faults as UNSAT without running SAT. Phase A fault ordering using net IDs is already in place.
6. Improve flow by integrating selected Yosys command capabilities into OpenTestability workflows.
7. Broaden distribution: a Nix flake install path is available now (nix run/nix profile install/nix develop); PyPI wheels and a nixpkgs submission are planned as the tool matures.

Legacy Verilog ("genus") mode

The gate-level Verilog input flow — historically called genus mode because the netlists came from Cadence Genus / Synopsys DC — was removed before 0.0.1. OpenTestability now ingests Yosys JSON only.

To use the old Verilog flow, build from the archived legacy-genus branch:

git checkout legacy-genus

That branch provides the full Verilog workflow: parse (pyverilog-based Verilog parsing), convert (text → JSON), dag, the standalone reconv/simple/advanced/ compare/visualize commands, and tpi, plus COP/SCOAP and test-point insertion over the parsed-file pipeline, emitting enhanced Verilog. See the Genus (Legacy Verilog) Mode guide for the complete command and option reference.

To stay on the current Yosys-only flow, convert Verilog to Yosys JSON first:

yosys -p "read_verilog design.v; synth; write_json design.json"

Contributing

Contributions are welcome. Start with CONTRIBUTING.md and open an issue for major proposals.

License

OpenTestability is licensed under Apache-2.0. See LICENSE.