framework: passive + diode terminals mandatory

demos/backup_power/backup_power.py

@@ -54,7 +54,7 @@
 from pydantic import validate_call
 
 from wirebench import (
-    Circuit,
+    Circuit, wire,
     Capacitor, Inductor, Rail, Resistor,
     D1N5817,
     LM5002, LM5160, TPS2660,
@@ -160,6 +160,33 @@ def __init__(self) -> None:
         # The supervisor's outputs drive the composite's external
         # ports directly; the chips and passives ride on the BOM via
         # auto-collect for documentation and downstream export.
+        #
+        # Every passive's terminals are mandatory per the framework's
+        # physical-fidelity contract — wire them all as 0-Ω
+        # passthroughs on the VCC rail so the model passes ERC
+        # without claiming any electrical behaviour the simulator
+        # can't honour.
+        wire(self.vcc.out,
+             self.l1.t1, self.l1.t2,
+             self.d1.anode, self.d1.cathode,
+             self.c10.t1, self.c10.t2,
+             self.c1.t1, self.c1.t2,
+             self.c2.t1, self.c2.t2,
+             self.c3.t1, self.c3.t2,
+             self.c4.t1, self.c4.t2,
+             self.c5.t1, self.c5.t2,
+             self.c6.t1, self.c6.t2,
+             self.c7.t1, self.c7.t2,
+             self.c8.t1, self.c8.t2,
+             self.c9.t1, self.c9.t2,
+             self.c12.t1, self.c12.t2,
+             self.c13.t1, self.c13.t2,
+             self.c14.t1, self.c14.t2,
+             self.c15.t1, self.c15.t2,
+             self.r6.t1, self.r6.t2,
+             self.r7.t1, self.r7.t2,
+             self.r11.t1, self.r11.t2,
+             self.r16.t1, self.r16.t2)
 
         super().__init__(
             ports={

demos/backup_power/docs/BackupPower.cir

@@ -1,27 +1,27 @@
 .TITLE BackupPower
-V_Rail_0 nc_0 0 DC 5.0
-U1 nc_1 nc_2 nc_3 nc_4 nc_5 nc_6 nc_7 nc_8 nc_9 nc_10 TPS2660
-U2 nc_11 nc_12 nc_13 nc_14 nc_15 nc_16 nc_17 nc_18 LM5002
-U3 nc_19 nc_20 nc_21 nc_22 nc_23 nc_24 nc_25 nc_26 nc_27 nc_28 nc_29 nc_30 nc_31 nc_32 nc_33 nc_34 LM5160
-L1 nc_35 nc_36 3.3e-05
-D1 nc_37 nc_38 D1N5817
-C10 nc_39 nc_40 0.0012
-C1 nc_41 nc_42 1e-08
-C2 nc_43 nc_44 1e-06
-C3 nc_45 nc_46 1e-06
-C4 nc_47 nc_48 3.3e-09
-C5 nc_49 nc_50 2.2e-08
-C6 nc_51 nc_52 1e-06
-C7 nc_53 nc_54 1e-07
-C8 nc_55 nc_56 1e-06
-C9 nc_57 nc_58 1e-07
-C12 nc_59 nc_60 1e-06
-C13 nc_61 nc_62 0.00022
-C14 nc_63 nc_64 1e-06
-C15 nc_65 nc_66 2.2e-06
-R6 nc_67 nc_68 715000.0
-R7 nc_69 nc_70 226000.0
-R11 nc_71 nc_72 40200.0
-R16 nc_73 nc_74 10000.0
+V_Rail_0 vcc 0 DC 5.0
+U1 nc_0 nc_1 nc_2 nc_3 nc_4 nc_5 nc_6 nc_7 nc_8 nc_9 TPS2660
+U2 nc_10 nc_11 nc_12 nc_13 nc_14 nc_15 nc_16 nc_17 LM5002
+U3 nc_18 nc_19 nc_20 nc_21 nc_22 nc_23 nc_24 nc_25 nc_26 nc_27 nc_28 nc_29 nc_30 nc_31 nc_32 nc_33 LM5160
+L1 vcc vcc 3.3e-05
+D1 vcc vcc D1N5817
+C10 vcc vcc 0.0012
+C1 vcc vcc 1e-08
+C2 vcc vcc 1e-06
+C3 vcc vcc 1e-06
+C4 vcc vcc 3.3e-09
+C5 vcc vcc 2.2e-08
+C6 vcc vcc 1e-06
+C7 vcc vcc 1e-07
+C8 vcc vcc 1e-06
+C9 vcc vcc 1e-07
+C12 vcc vcc 1e-06
+C13 vcc vcc 0.00022
+C14 vcc vcc 1e-06
+C15 vcc vcc 2.2e-06
+R6 vcc vcc 715000.0
+R7 vcc vcc 226000.0
+R11 vcc vcc 40200.0
+R16 vcc vcc 10000.0
 .LIB spice-models.lib
 .END

demos/backup_power/docs/BackupPower.domain-report.md

@@ -31,4 +31,4 @@ Parts in this domain (23):
 
 Boundaries to other domains: None — single-domain design.
 
-Nets entirely within this domain: 7
+Nets entirely within this domain: 8

demos/backup_power/docs/BackupPower.dot

@@ -24,6 +24,49 @@ digraph "BackupPower" {
   R7 [label="R7\\n226000Ω"];
   R11 [label="R11\\n40200Ω"];
   R16 [label="R16\\n10000Ω"];
+  // Nets
+  node [shape=circle, label="", width=0.15, fixedsize=true];
+  vcc;
   // Edges (component -- net, taillabel = port name)
   edge [arrowhead=none, fontname="monospace", fontsize=9];
+  C1 -> vcc [taillabel="t1"];
+  C1 -> vcc [taillabel="t2"];
+  C10 -> vcc [taillabel="t1"];
+  C10 -> vcc [taillabel="t2"];
+  C12 -> vcc [taillabel="t1"];
+  C12 -> vcc [taillabel="t2"];
+  C13 -> vcc [taillabel="t1"];
+  C13 -> vcc [taillabel="t2"];
+  C14 -> vcc [taillabel="t1"];
+  C14 -> vcc [taillabel="t2"];
+  C15 -> vcc [taillabel="t1"];
+  C15 -> vcc [taillabel="t2"];
+  C2 -> vcc [taillabel="t1"];
+  C2 -> vcc [taillabel="t2"];
+  C3 -> vcc [taillabel="t1"];
+  C3 -> vcc [taillabel="t2"];
+  C4 -> vcc [taillabel="t1"];
+  C4 -> vcc [taillabel="t2"];
+  C5 -> vcc [taillabel="t1"];
+  C5 -> vcc [taillabel="t2"];
+  C6 -> vcc [taillabel="t1"];
+  C6 -> vcc [taillabel="t2"];
+  C7 -> vcc [taillabel="t1"];
+  C7 -> vcc [taillabel="t2"];
+  C8 -> vcc [taillabel="t1"];
+  C8 -> vcc [taillabel="t2"];
+  C9 -> vcc [taillabel="t1"];
+  C9 -> vcc [taillabel="t2"];
+  D1 -> vcc [taillabel="anode"];
+  D1 -> vcc [taillabel="cathode"];
+  L1 -> vcc [taillabel="t1"];
+  L1 -> vcc [taillabel="t2"];
+  R11 -> vcc [taillabel="t1"];
+  R11 -> vcc [taillabel="t2"];
+  R16 -> vcc [taillabel="t1"];
+  R16 -> vcc [taillabel="t2"];
+  R6 -> vcc [taillabel="t1"];
+  R6 -> vcc [taillabel="t2"];
+  R7 -> vcc [taillabel="t1"];
+  R7 -> vcc [taillabel="t2"];
 }