I'm an undergraduate student at UIT-VNUHCM, currently in the IC Design Talent Program

• My main technical focus is VLSI / SoC Design, especially RTL Design, FPGA-based acceleration, and Design for Testability (DFT).
• I am actively researching and developing hardware accelerators for NIST-standardized Post-Quantum Cryptography (ML-KEM, ML-DSA, and SLH-DSA), aiming for PPA-efficient RTL implementations on FPGAs.
• I also have a secondary interest in RFIC.
• I am expanding my system-level perspective through HW/SW co-design, working with RISC-V ecosystems and AI accelerators.
• Languages I use: Verilog, SystemVerilog, Tcl, C, C++, Python.

• First Prize – UIT Net Challenge 2025
• Finalist – Makerthon 2025
• Honorable Mention – Annual Microelectronics Olympiad (AMO) 2026 – National Round

Hardware accelerator for ML-KEM (Kyber) Number Theoretic Transform (NTT) focusing on throughput and energy efficiency.

• Architecture: Single-PE, 1-cycle/Butterfly pipeline.
• Optimizations: Memory conflict-free banking for parallel dual-element access in a single clock cycle. Handled pipeline drain delays and timing alignment.
• Performance: 906 cycles for NTT; 1162 cycles for INTT.
• Efficiency: Sustains 1 BF/cycle with 10 cycles of pipeline overhead (startup & drain latency), achieving 98.9% theoretical throughput efficiency.

Resource-optimized SHAKE256 cryptographic accelerator deployed on Xilinx Artix-7 (xc7a100t).

• Throughput: 4.66 Gbps at 205.46 MHz. 3.5x faster than the reference design in Design of an Energy-Efficient SHA-3 Accelerator on Artix-7 FPGA for Secure Network Application (DOI: 10.3390/computers15010003).
• Resource Utilization: 5,274 LUTs, 6,514 FFs. Requires 0 BRAMs and 0 DSPs (2.9x fewer LUTs and 3.5x fewer FFs than the reference).
• Energy Efficiency: 9.45 Gbps/W (5.5x improvement) with 0.493W total power (37% reduction).